TMPM363F10FG Toshiba, TMPM363F10FG Datasheet - Page 615

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TMPM363F10FG

Manufacturer Part Number
TMPM363F10FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMPM363F10FG

Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
100
Package
LQFP(14x14)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
4
Uart/sio (ch)
5
Usb
Host
Can
1
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
8
10-bit Ad Converter
8
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
Y
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMPM363F10FG
Manufacturer:
Toshiba
Quantity:
10 000
7. When Port Reset is executed while generating Babble, Port keep disable state. Port Reset sequence is below.
8. When Scheduling Overrun is occurred while executing Full-Speed Isochronous transfer, It may be gener-
9. The data received from the USB device is written to a specified internal RAM through the BUS-I/F as re-
ated the Unrecoverable Error. When Unrecoverable Error was generated, recover from Unrecoverable Er-
ror by software reset.
ceive buffer; however, data is not written to the internal RAM under the conditions shown below. Align
the starting address to be multiple of 4, do not specify the address starting from 4n+1 of receiving buffer.
4n indicates the address aligned to 4 bytes.
<Condition ignored write accesses>
Write accesses are ignored when the conditions below are all satisfied.
(Example)
1
2
3
4
5
6
7
1. The received data is MPS (Max Packet Size)×n+2
2. The last 2 bytes of the write buffer address are 4n+1 and 4n+2.
HcRhPortStatus1
Detect of HW interrupt
HcRhPortStatus1
HcRhPortStatus1
HcRhPortStatus1
Clear of HW interrupt
HcRhPortStatus1
Detect if HW interrupt
HcRhPortStatus1
HcRhPortStatus1
HcRhPortStatus1
<PRS>
<PRSC>
<PES>
<CCS>
<PRS>
<PRSC>
<PES>
<CCS>
Page 589
=
=
=
=
=
=
=
=
1
1
0
1
1
1
1
1
(Write)
(Read)
(Write)
(Read)
: Excute port reset
: Port is an invalid state.
: Retry port reset
: Port is a valid state.
TMPM363F10FG

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