TMPM363F10FG Toshiba, TMPM363F10FG Datasheet - Page 53

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TMPM363F10FG

Manufacturer Part Number
TMPM363F10FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMPM363F10FG

Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
100
Package
LQFP(14x14)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
4
Uart/sio (ch)
5
Usb
Host
Can
1
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
8
10-bit Ad Converter
8
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
Y
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMPM363F10FG
Manufacturer:
Toshiba
Quantity:
10 000
5. Reset
5.1
700 μs or more for stable
The case where it takes
setting <SYSRESETREQ> in the Application Interrupt and Reset Control Register.
TMPM363F10FG, the internal regulator requires at least 700 μs to be stable.
kept "Low" for a duration of time sufficiently long enough for the internal regulator and oscillator to be stable.
RVDD3,
DVDD3A,
DVDD3B,
AVDD3
RESET
(External reset)
High-speed oscillation
Internal reset
RESET
(External reset)
High-speed oscillation
Internal reset
The TMPM363F10FG has three reset sources: an external reset pin (RESET), a watchdog timer (WDT) and the
For reset from the WDT, refer to the chapter on the WDT.
For reset from <SYSRESETREQ>, refer to "Cortex-M3 Technical Reference Manual".
Cold reset
The power-on sequence must consider the time for the internal regulator and oscillator to be stable. In the
The time required to achieve stable oscillation varies with system. At cold reset, the external reset pin must be
After the external reset (RESET) signal is released, the internal reset signal remains asserted for a further 400μs.
Figure 5-1 shows the power-on sequence.
Note:Do not reset with <SYSRESETREQ> in SLOW mode.
oscillation
2.7 V
0 V
0.1ms/V
(min.)
Figure 5-1 Cold Reset Sequence
700 μs(min.)
Page 27
12 cycle (min.)
12 cycle(min.)
400 μs(min.)
400 μs(min.)
TMPM363F10FG

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