TMPM363F10FG Toshiba, TMPM363F10FG Datasheet - Page 575
TMPM363F10FG
Manufacturer Part Number
TMPM363F10FG
Description
Manufacturer
Toshiba
Datasheet
1.TMPM363F10FG.pdf
(788 pages)
Specifications of TMPM363F10FG
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
100
Package
LQFP(14x14)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
4
Uart/sio (ch)
5
Usb
Host
Can
1
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
8
10-bit Ad Converter
8
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
Y
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
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17.4.1.4
17.4.1.5
17.4.1.6
RMCRCR3 and RMCRCR4 registers, RMC is ready for reception. Detecting a leader initiates reception.
width is shorter than a maximum low width of leader detection specified in the RMCRCR1 <RMCLLMAX
[7:0]> bits. RMC keeps receiving data until the final data bit is received.
ta bit determination of 0 or 1 are applied regardless of whether a signal has a leader or not.
By enabling the RMCREN <RMCREN> bit after configuring the RMCRCR1, RMCRCR2,
RMC stops reception by clearing the RMCREN <RMCREN> bit to "0" (reception disabled).
Clearing this bit during reception stops reception immediately and the received data is discarded.
Setting RMCRCR2 <RMCLD> enables RMC to receive signals with or without a leader.
By setting RMCRCR2 <RMCLD>, RMC starts receiving data if it recognizes a signal of which low
If RMCRCR2 <RMCLD> is enabled, the same settings of error detection, reception completion and da-
Thus receivable remote control signals are limited.
Note:Changing the configurations of the RMCRCR1, RMCRCR2, RMCRCR3 and RMCRCR4 registers dur-
Enabling Reception
Stopping Reception
Receiving Remote Control Signal without Leader in Waiting Leader
Waiting for leader
RMCRCR2<RMCLD> = 1
ing reception may harm their proper operation. Be careful if you change them during reception.
Leader waveform
Maximum data bit cycle <RMCDMAX[7:0]>
Minimum low width <RMCLLMIN[7:0]>
Maximum data bit cycle is detected if a signal stays
low shorter than specified and longer than a maximum
data bit cycle.
Page 549
RMC starts receiving data by receiving a signal which
is less than the minimum low pulse width.
TMPM363F10FG
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