TMPM363F10FG Toshiba, TMPM363F10FG Datasheet - Page 768

• Manufacturer Part Number: TMPM363F10FG
• Manufacturer: Toshiba

Specifications of TMPM363F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 4
• Uart/sio (ch): 5
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: 8
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

27.6
AC Electrical Characteristics
27.6.4
27.6.4.1
SCL clock frequency
Hold time for a START condition
SCL Low width (input) (Note1)
SCL high width (input) (Note2)
Setup time for a repeated START condition
Data hold time (input) (Note3, 4)
Data setup time
Setup time for a STOP condition
Bus free time between STOP condition
and START condition
Note 1: SCL clock Low width (output) : (2
Note 2: SCL clock High width (output) : (2
Note 3: The output data hold time is equal to 12x of internal SCL.
Note 4: The Philips I2C-bus specification states that a device must internally provide a hold time of at least 300 ns
Note 5: Software dependent
Note 6: The Philips I2C-bus specification instructs that if the power supply to a Fast-mode device is switched off, the SDA
SCL
SDA
fsys cycle time. It varies depending on the programming of the clock gear function.
Serial Bus Interface (I2C/SIO)
On I2C-bus specification, Maximum Speed of Standard Mode is 100kHz, Fast mode is 400khz. Internal SCL frequen-
cy setting should comply with Note1 & Note2 shown above.
for the SDA signal to bridge the undefined region of the falling edge of SCL. However, this SBI does not satis-
fy this requirement. Also, the output buffer for SCL does not incorporate slope control of the falling edges;
therefore, the equipment manufacturer should design so that the input data hold time shown in the table is sat-
isfied, including tr/tf of the SCL and SDA lines.
and SCL I/O pins must be floating so that they don't obstruct the bus lines. However, this SBI does not satisfy this re-
quirement.
In the table below, the letter x represents the I2C operation clock cycle time which is identical to the
n denotes the value of n programmed into the SCK (SCL output frequency select) field in the SBIxCR.
I2C Mode
Parameter
S: START condition
Sr: RESTART condition
P: STOP condition
t
HD;STA
S
t
f
t
LOW
t
SU;DAT
t
SCL
t
r
t
t
t
t
t
Symbol
HD; STA
HD; DAT
SU; DAT
SU; STO
SU; STA
t
t
t
t
HIGH
LOW
SCL
BUF
t
HIGH
n − 1
n − 1
+ 58)/x
+ 12)/x
(Note5)
(Note5)
t
Min
HD;DAT
−
−
−
−
−
−
0
Page 742
Equation
Max
−
−
−
−
−
−
−
−
−
Standard Mode
Min
250
4.0
4.7
4.0
4.7
0.0
4.0
4.7
0
t
Sr
SU;STA
Max
100
−
−
−
−
−
−
−
−
t
SU;STO
100
Min
0.6
1.3
0.6
0.6
0.0
0.6
1.3
0
Fast Mode
P
t
BUF
TMPM363F10FG
Max
400
−
−
−
−
−
−
−
−
Unit
kHz
μs
μs
μs
μs
μs
ns
μs
μs