TMPM363F10FG Toshiba, TMPM363F10FG Datasheet - Page 620

• Manufacturer Part Number: TMPM363F10FG
• Manufacturer: Toshiba

Specifications of TMPM363F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 4
• Uart/sio (ch): 5
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: 8
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

19.3
Operations
19.3
19.3.1
19.3.2
Operations
Detecting time can be selected between 2
ing time as specified is elapsed, the watchdog timer interrupt (INTWDT) generates, and the watchdog timer
out pin (WDTOUT) output "Low".
of the watchdog timer should be cleared by software instruction before INTWDT interrupt generates. If the bi-
nary counter is not cleared, the non-maskable interrupt generates by INTWDT. Thus CPU detects malfunc-
tion (runway), malfunction countermeasure program is performed to return to the normal operation.
the watchdog timer out pin to reset pins of peripheral devices.
low modes, the watchdog timer should be disabled.
The Watchdog timer is consists of the binary counters that work using the system clock (fsys) as an input.
To detect malfunctions (runaways) of the CPU caused by noise or other disturbances, the binary counter
Additionally, it is possible to resolve the problem of a malfunction (runaway) of the CPU by connecting
The watchdog timer begins operation immediately after a reset is cleared.
If not using the watchdog timer, it should be disabled.
The watchdog timer cannot be used as the high-speed frequency clock is stopped. Before transition to be-
In IDLE mode, its operation depends on the WDMOD <I2WDT> setting.
Also, the binary counter is automatically stopped during debug mode.
Basic Operation
Operation Mode and Status
-
-
-
-
-
STOP mode
SLEEP mode
SLOW mode
BACKUP STOP mode
BACKUP SLEEP mode
15
, 2
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17
, 2
19
, 2
21
, 2
23
and 2
25
by the WDMOD<WDTP[2:0]>. The detect-
TMPM363F10FG