TMPM363F10FG Toshiba, TMPM363F10FG Datasheet - Page 281

• Manufacturer Part Number: TMPM363F10FG
• Manufacturer: Toshiba

Specifications of TMPM363F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 4
• Uart/sio (ch): 5
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: 8
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

11-0
Bit
TransferSize
[11:0]
Note 1: The burst size to be set with DBsize and SBsize has nothing to do with the HBURST for the AHB bus.
Bit Symbol
<Dwidth[2:0]> /
<Swidth[2:0]>
<DBSize[2:0]> /
<SBSize[2:0]>
R/W
Type
Set the total number of transfers.
Set the total number of data transfers in the units of data bit width (4bytes/2bytes/1byte) defined as that of
the transfer source.
The burst size indicates only the total amount of data to be transferred per internal DMA request. Thus as
long as the bit width of transfer source and the total number of transfers are not changed, the total amount
of transfer data is not changed even if the burst size is changed.
The <TransferSize> value decrements with respect to each DMA transfer until it reaches 0.
On read, the number of transfers yet to be performed is read.
The total number of transfers is used as the unit for the transfer source bit width.
Set the number so that the following expression is satisfied:
Transfer source bit width × Total number of transfers = Transfer destination bit width × N (N : Integer number)
(ex.1) Bit width of transfer source:8 bit, bit width of transfer destination:32 bit, total number of transfers:25
times
(ex.2) Bit width of transfer source :32 bit, bit width of transfer destination:16 bit, total number of transfers:
13 times
When peripheral to memory transfer or memory to peripheral transfer is performed, peripheral circuits gen-
erates DMA request signal to indicate the preparation is ready. This signal triggers to execute data trans-
fers. (In the case of memory to memory transfers, only software start is used.)
Set the burst size to define the amount of data transferred from peripherals per DMA request signal. This reg-
ister is used with FIFO buffer that can be contained multiple data.
For example:
When <Swidth>="000"Åi8bit), the number of transfers is expressed in the units of byte.
When <Swidth>="001"Åi16bit), the number of transfers is expressed in the units of half word.
When <Swidth>="010"Åi32bit), the number of transfers is expressed in the units of word.
8 bit × 25 times = 200 bit (25 byte)
N = 200 ÷ 32 = 6.25 word
Since 6.25 is not an integer number, the above setting is invalid.
If the transfer source bit width is smaller than the transfer destination bit width, care must be taken
when setting the total number of transfers.
32 bit × 13 times = 416 bit (13 word)
N = 416 ÷ 16 = 26 half_word
Since 26 is an integer number, the above setting is valid.
Page 255
Description
TMPM363F10FG