TMPM363F10FG Toshiba, TMPM363F10FG Datasheet - Page 22

• Manufacturer Part Number: TMPM363F10FG
• Manufacturer: Toshiba

Specifications of TMPM363F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 4
• Uart/sio (ch): 5
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: 8
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

21. Backup module
22. Analog / Digital Converter (ADC)
23. Real Time Clock (RTC)
xiv
21.1 Features................................................................................................................................613
21.2 Block Diagram.....................................................................................................................613
21.3 BACKUP Mode Operation.................................................................................................614
22.1 Outline.................................................................................................................................619
22.2 Configuration.......................................................................................................................620
22.3 Registers..............................................................................................................................621
22.4 Description of Operations...................................................................................................642
23.1 Function...............................................................................................................................651
23.2 Block Diagram.....................................................................................................................651
23.3 Detailed Description Register.............................................................................................652
21.3.1
22.3.1
22.3.2
22.3.3
22.3.4
22.3.5
22.3.6
22.3.7
22.3.8
22.3.9
22.3.10
22.3.11
22.3.12
22.3.13
22.3.14
22.3.15
22.3.16
22.3.17
22.3.18
22.3.19
22.3.20
22.4.1
22.4.2
22.4.3
22.4.4
22.4.5
23.3.1
21.3.1.1
21.3.1.2
21.3.1.3
21.3.1.4
22.4.2.1
22.4.2.2
22.4.5.1
22.4.5.2
22.4.5.3
22.4.5.4
22.4.5.5
22.4.5.6
22.4.5.7
Operable peripherals in the BACKUP mode................................................................................................................614
Register list....................................................................................................................................................................621
ADCBAS (Conversion Accuracy Setting Register).....................................................................................................622
ADCLK (Conversion Clock Setting Register).............................................................................................................623
ADMOD0 (Mode Control Register 0)..........................................................................................................................625
ADMOD1 (Mode Control Register 1)..........................................................................................................................626
ADMOD2 (Mode Control Register 2) .........................................................................................................................627
ADMOD3 (Mode Control Register 3)..........................................................................................................................629
ADMOD4 (Mode Control Register 4) .........................................................................................................................630
ADMOD5 (Mode Control Register 5)..........................................................................................................................631
Analog Reference Voltage............................................................................................................................................642
AD Conversion Mode...................................................................................................................................................642
AD Monitor Function....................................................................................................................................................643
Selecting the Input Channel..........................................................................................................................................644
AD Conversion Details.................................................................................................................................................644
Register List...................................................................................................................................................................652
ADREG08 (Conversion Result Register 08)..............................................................................................................632
ADREG19 (AD Conversion Result Register 19).......................................................................................................633
ADREG2A (AD Conversion Result Register 2A).....................................................................................................634
ADREG3B (AD Conversion Result Register 3B)......................................................................................................635
ADREG4C (AD Conversion Result Register 4C)......................................................................................................636
ADREG5D (AD Conversion Result Register 5D).....................................................................................................637
ADREG6E (AD Conversion Result Register 6E)......................................................................................................638
ADREG7F (AD Conversion Result Register 7F).......................................................................................................639
ADREGSP (AD Conversion Result Register SP)......................................................................................................640
ADCMP0 (AD Conversion Result Comparison Register 0)......................................................................................641
ADCMP1 (AD Conversion Result Comparison Register 1)......................................................................................641
Transition to the BACKUP mode
Backup Transition Flow
Transition Flowchart
BACKUP Mode Timing Chart
Normal AD conversion
Top-priority AD conversion
Starting AD Conversion
AD Conversion
Top-priority AD conversion during normal AD conversion
Stopping Repeat Conversion Mode
Reactivating normal AD conversion
Conversion completion
Interrupt generation timings and AD conversion result storage register