TMPM363F10FG Toshiba, TMPM363F10FG Datasheet - Page 503

• Manufacturer Part Number: TMPM363F10FG
• Manufacturer: Toshiba

Specifications of TMPM363F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 4
• Uart/sio (ch): 5
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: 8
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

16. CAN Controller
16.1
This product includes one channel of CAN controller.
Overview
・ Compliant with CAN version 2.0 B (active)
・ Standard and extended formats supported
・ Data frames and remote frames supported for each format
・ 32 Mailboxes (31 receive and transmit, 1 receive only)
・ CAN bus baud rate up to 1 Mbps (with a system clock of at least 48 MHz)
・ Bit timing parameter equivalent to Intel 82527 ™
・ Baud rate prescaler built in
・ The order in which messages are transmitted can be selected from the following two types of internal arbi-
・ Time stamp function for receive and transmit messages
・ Operation modes
・ Message receive mask function for two systems
・ Receive mask bit for ID extension bit
・ Interrupt signal
trations :
-
-
-
-
Normal operation mode
Configuration mode
Sleep mode
Suspend mode
Test loop back mode
Test error mode
INTCANRX
INTCANTX
INTCANGB
The mailbox with the lower number will be sent first
The mailbox with the higher priority identifier will be sent first
Programmable global receive mask (common to mailboxes 0 to 31)
Programmable local receive mask (for mailbox 31 only)
CAN walk-up with CAN bus active state detection (at CANMCR<WUBA>
="1") or a write access to the master control register MCR
Inactive state on the CAN bus
Self acknowledge
Writable error counters
: CAN receive completion interrupt
: CAN transmit completion interrupt
: CAN global interrupt
Interrupt from eight causes including warning level, error passive and bus-
off interrupts)
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TMPM363F10FG