ade7169f16 Analog Devices, Inc., ade7169f16 Datasheet - Page 103

• Manufacturer Part Number: ade7169f16
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc And Lcd Driver
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
TIMERS
The ADE7169F16 has three 16-bit timer/ counters: Timer 0,
Timer 1, and Timer 2. The timer/counter hardware is included
on-chip to relieve the processor core of the overhead inherent in
implementing timer/counter functionality in software. Each
timer/counter consists of two 8-bit registers: THx and TLx (x =
0, 1, or 2). All three can be configured to operate either as
timers or as event counters.
When functioning as a timer, the TLx register is incremented
every machine cycle. Thus, one can think of it as counting
machine cycles. Because a machine cycle on a single-cycle core
consists of one core clock period, the maximum count rate is
the core clock frequency.
Table 93. Timer SFRs
SFR
TCON
TMOD
TL0
TL1
TH0
TH1
T2CON
RCAP2L
RCAP2H
TL2
TH2
TIMER SFR REGISTER LIST
Table 94. Timer/Counter 0 and 1 Mode SFR (TMOD, 0x89)
Bit
Location
7
6
5-4
Address
0x88
0x89
0x8A
0x8B
0x8C
0x8D
0xC8
0xCA
0xCB
0xCC
0xCD
Bit
Mnemonic
Gate1
C_T1
T1_M1,
T1_M0
Bit Addressable
Yes
No
No
No
No
No
Yes
No
No
No
No
0
Default
Value
0
00
Description
Timer 1 Gating Control.
Set by software to enable Timer/Counter 1 only while the INT1 pin is high and the TR1 control is
set.
Cleared by software to enable Timer 1 whenever the TR1control bit is set.
Timer 1 Timer or Counter Select Bit.
Set by software to select counter operation (input from T1 pin).
Cleared by software to select the timer operation (input from internal system clock).
Timer 1 Mode Select bits
M1
0
0
Description
Timer0 and Timer1 Control Register – see Table 95
Timer Mode register– see Table 94
Timer0 LSB– see Table 98
Timer1 LSB– see Table 100
Timer0 MSB– see Table 97
Timer1 MSB– see Table 99
Timer2 Control Register – see Table 96
Timer2 Reload/Capture LSB – see Table 104
Timer2 Reload/Capture MSB – see Table 103
Timer2 LSB – see Table 102
Timer2 MSB – see Table 101
M0
0
1
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Description
TH1 operates as an 8-bit timer/counter. TL1 serves as 5-bit prescaler.
16-Bit Timer/Counter. TH1 and TL1 are cascaded; there is no prescaler.
When functioning as a counter, the TLx register is incremented
by a 1-to-0 transition at its corresponding external input pin:
T0, T1, or T2. When the samples show a high in one cycle and a
low in the next cycle, the count is incremented. Because it takes
two machine cycles (two core clock periods) to recognize a
1-to-0 transition, the maximum count rate is half the core clock
frequency.
There are no restrictions on the duty cycle of the external input
signal, but, to ensure that a given level is sampled at least once
before it changes, it must be held for a minimum of one full
machine cycle. User configuration and control of all timer
operating modes is achieved via the SFRs in Table 93.
ADE7169F16