ade7169f16 Analog Devices, Inc., ade7169f16 Datasheet - Page 88

• Manufacturer Part Number: ade7169f16
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc And Lcd Driver
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
LCD DRIVER
The LCD module is capable of directly driving an LCD panel of
24 x 4 segments without compromising any ADE7169F16
functionalities. Using shared pins, the driver can accommodate
an LCD with up to 26 x 4 segments. It is capable of driving
LCDs with 2x, 3x and 4x multiplexing. LCD waveform voltages
generated through internal charge pump circuitry support up to
5V LCDs. An external resistor ladder for LCD waveform
voltage generation is also supported.
The ADE7169F16 has an embedded LCD control circuit, LCD
driver and power supply circuit. The LCD module is functional
in all Operating modes.
Table 70. LCD Driver SFRs
Table 71. LCD Configuration SFR (LCDCON, 0x95)
address
Bit
Location
7
6
5
4
3
2
1-0
0xAC
0xAE
0xED
(hex)
0x9C
0xB1
0x95
0x96
0x97
SFR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Mnemonic
LCDEN
LCDRST
BLINKEN
LCDPSM2
CLKSEL
BIAS
LMUX[1:0]
LCDCONX
LCDCONY
LCDSEGE2
LCDSEGE
LCDCON
LCDDAT
LCDCLK
LCDPTR
Name
0
0
0
0
Default
Value
0
0
0
LCD Configuration SFR
LCD Segment Enable 2
LCD Configuration X
LCD Configuration Y
LCD Segment Enable
LCD Pointer
Description
LCD Clock
LCD Data
Force LCD off when in PSM2 (Sleep mode).
Bias Mode
LCD Multiplex level
Description
LCD enable.
If this bit is set, the LCD driver is enabled.
LCD data registers are reset to zero.
If this bit is set, the LCD data registers will be reset to zero.
Blink Mode enable bit.
If this bit is set, blink mode is enabled. The blink mode is configured by the
BLKMOD[1:0] and BLKFREQ[1:0] bits in the LCD Clock SFR (LCDCLK, 0x96)
LCD clock selection
0
1
0
1
0
1
Rev. PrD | Page 88 of 140
The LCD is disabled or enabled in PSM2 by LCDEN bit.
The LCD is disabled in PSM2 regarless of LCDEN setting.
1/2
1/3
LCD SFR REGISTER LIST
There are six LCD control registers that configure the driver for
the specific type of LCD in the end system and set up the user
display preferences. The LCD Configuration SFR (LCDCON,
0x95), LCD Configuration X SFR (LCDCONX, 0x9C) and LCD
Configuration Y SFR (LCDCONY, 0xB1) SFRs contains general
LCD driver configuration information including the LCD
enable and reset, as well as method of LCD voltage generation
and the multiplex level. The LCD Clock SFR (LCDCLK, 0x96)
configures timing settings for LCD frame rate and blink rate.
LCD pins are configured for LCD functionality in the LCD
Segment Enable SFR (LCDSEGE, 0x97) and LCD Segment
Enable 2 SFR (LCDSEGE2, 0xED).
f
2048Hz
128Hz
LCDCLK
ADE7169F16