ade7169f16 Analog Devices, Inc., ade7169f16 Datasheet - Page 117

• Manufacturer Part Number: ade7169f16
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc And Lcd Driver
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
4
3
2
1
0
Table 117. Serial port Buffer SFR (SBUF, 0x99)
Bit
Location
7-0
Table 118. Enhanced Serial baud rate control SFR (SBAUDT, 0x9E)
Bit
Location
7
6
5
4-3
2, 1, 0
Bit
Mnemonic
SBUF
0x9C
0x9B
0x9A
0x99
0x98
Bit
Mnemonic
OWE
FE
BE
SBTH1, SBTH0
DIV2, DIV1,
DIV0
REN
TB8
RB8
TI
RI
Default
Value
0
Default
Value
0
0
0
0
0
0
0
0
0
0
Description
Serial port data buffer
Description
Overwrite Error. This bit is set when new data is received and RI=1. It indicates that
SBUF was not read before the next character was transferred in, causing the prior
SBUF data to be lost.
Frame Error. This bit is set when the received frame did not have a valid stop bit. This
bit is read only and updated every time a frame is received.
Break Error. This bit is set whenever the receive data line (Rx) is low for longer than a
full transmission frame, the time required for a start bit, 8 data bits, a parity bit and half
a stop bit. This bit is updated every time a frame is received.
Extended divider ratio for baud rate setting as shown in Table 120
Binary Divider
DIV2
0
0
0
0
1
1
1
1
In Modes 2 or 3, if SM2 is set, RI is not activated if the received ninth data bit in RB8 is
0. If SM2 is cleared, RI is set as soon as the byte of data is received.
Serial Port Receive Enable Bit.
Set by user software to enable serial port reception.
Cleared by user software to disable serial port reception.
Serial Port Transmit (Bit 9).
The data loaded into TB8 is the ninth data bit transmitted in Modes 2 and 3.
Serial Port Receiver Bit 9.
The ninth data bit received in Modes 2 and 3 is latched into RB8. For Mode 1, the stop
bit is latched into RB8.
Serial Port Transmit Interrupt Flag.
Set by hardware at the end of the eighth bit in Mode 0, or at the beginning of the stop
bit in Modes 1, 2, and 3.
TI must be cleared by user software.
Serial Port Receive Interrupt Flag.
Set by hardware at the end of the eighth bit in Mode 0, or halfway through the stop bit
in Modes 1, 2, and 3.
RI must be cleared by user software.
DIV1
0
0
1
1
0
0
1
1
Rev. PrD | Page 117 of 140
DIV0
0
1
0
1
0
1
0
1
Divide by 1. See Table 120.
Divide by 2. See Table 120.
Divide by 4. See Table 120.
Divide by 8. See Table 120.
Divide by 16. See Table 120.
Divide by 32. See Table 120.
Divide by 64. See Table 120.
Divide by 128. See Table 120.
ADE7169F16