ade7169f16 Analog Devices, Inc., ade7169f16 Datasheet - Page 119

• Manufacturer Part Number: ade7169f16
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc And Lcd Driver
• Manufacturer: Analog Devices, Inc.

(SHIFT CLOCK)
Preliminary Technical Data
UART OPERATION MODES
Mode 0 (Shift Register with baud rate fixed at
Fcore /12)
Mode 0 is selected when the SM0 and SM1 bits in the SCON
SFR are clear. In this shift register mode, serial data enters and
exits through RxD. TxD outputs the shift clock. The baud rate is
fixed at F
Transmission is initiated by any instruction that writes to SBUF.
The data is shifted out of the RxD line. The 8 bits are
transmitted with the least significant bit (LSB) first.
Reception is initiated when the receive enable bit (REN) is 1
and the receive interrupt bit (RI) is 0. When RI is cleared, the
data is clocked into the RxD line, and the clock pulses are
output from the TxD line as shown in Figure 76.
Mode 1 (8-Bit UART, Variable Baud Rate)
Mode 1 is selected by clearing SM0 and setting SM1. Each data
byte (LSB first) is preceded by a start bit (0) and followed by a
stop bit (1). Therefore, each frame consists of 10 bits
transmitted on TxD or received on RxD.
The baud rate is set by a timer overflow rate. Timer 1 or Timer
2 can be used to generate baud rates or both timers can be used
simultaneously where one generates the transmit rate and the
other generates the receive rate. There is also a dedicated timer
for baud rate generation, UART Timer, which has a fractional
divisor to precisely generate any baud rate—see the UART
Timer Generated Baud Rates section.
Transmission is initiated by a write to SBUF. Next a stop bit (a
1) is loaded into the 9th bit position of the transmit shift
register. The data is output bit-by-bit until the stop bit appears
on TxD and the transmit interrupt flag (TI) is automatically set
as shown in Figure 77.
(SCON.1)
(DATA OUT)
TxD
TI
300
300
300
300
300
300
300
300
RxD
TxD
core
START
BIT
/12. Eight data bits are transmitted or received.
DATA BIT 0
D0
Figure 76. 8-Bit Shift Register Mode
D1
D2
DATA BIT 1
D3
0
1
2
3
4
5
6
7
D4
D5
DATA BIT 6
I.E., READY FOR MORE DATA
2
1
0
0
0
0
0
0
D6
SET INTERRUPT
D7
DATA BIT 7
STOP BIT
7
7
7
6
5
4
3
2
Rev. PrD | Page 119 of 140
17H
0FH
07H
06H
05H
04H
03H
02H
Reception is initiated when a 1-to-0 transition is detected on
RxD. Assuming that a valid start bit is detected, character
reception continues. The 8 data bits are clocked into the serial
port shift register.
All of the following conditions must be met at the time the final
shift pulse is generated to receive a character:
If any of these conditions are not met, the received frame is
irretrievably lost, and the receive interrupt flag, RI, is not set.
If the received frame has met the above criteria, the following
events occur:
Mode 2 (9- bit UART with baud fixed at F
or F
Mode 2 is selected by setting SM0 and clearing SM1. In this
mode, the UART operates in 9-bit mode with a fixed baud rate.
The baud rate is fixed at F
the SMOD bit in PCON, the frequency can be doubled to
F
data bits, a programmable 9th bit, and a stop bit (1). The 9th bit
is most often used as a parity bit or as part of a multiprocessor
communication protocol, although it can be used for anything,
including a ninth data bit if required.
To use the 9
core
/32. Eleven bits are transmitted or received: a start bit (0), 8
If the extended UART is disabled (EXTEN=0 in the CFG
SFR), RI must be zero to receive a character. This ensures
that the data in SBUF will not be overwritten if the last
received character has not been read.
If frame error checking is enabled by setting SM2, the
received stop bit must be set to receive a character. This
ensures that every character received comes from a valid
frame, with both a start and a stop bit)
The 8 bits in the receive shift register are latched into SBUF.
The 9th bit (stop bit) is clocked into RB8 in SCON.
The receiver interrupt flag (RI) is set.
core
/32)
th
data bit as part of a communication protocol for a
Figure 77. 8-Bit Variable Baud Rate
ABH
ABH
ABH
ABH
ABH
ABH
ABH
ABH
core
/64 by default, although by setting
- 0.31
- 0.31
- 0.31
- 0.31
- 0.31
- 0.31
- 0.31
- 0.31
ADE7169F16
core
/64