ade7169f16 Analog Devices, Inc., ade7169f16 Datasheet - Page 76

• Manufacturer Part Number: ade7169f16
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc And Lcd Driver
• Manufacturer: Analog Devices, Inc.

ADE7169F16
This number is referred to as a literal because it refers only to a
value and not to a memory location. Instructions using this
addressing mode will be slower than those between two
registers since the literal must be stored and fetched from
memory. The expression can be entered as a symbolic variable
or an arithmetic expression; the value will be computed by the
assembler.
Direct Addressing: With Direct Addressing, the value at the
source address is moved to the destination address. Direct
Addressing provides the fastest execution time of all the
addressing modes when an instruction is performed between
registers using direct addressing. Note that indirect or direct
addressing modes can be used to access general purpose RAM
addresses 0x00 through 0x7F. An instruction with direct
addressing that uses an address between 0x80 and 0xFF is
referring to a special function memory location.
Indirect Addressing: With Indirect Addressing, the value
pointed to by the register is moved to the destination address.
For example, to move the contents of internal RAM address 82h
to the accumulator:
MOV
MOV
The two instructions above require a total of four clock cycles
and three bytes of storage in the program memory.
Indirect addressing allows addresses to be computed, and is
useful for indexing into data arrays stored in RAM.
Note that an instruction that refers to addresses 00 through 7Fh
is referring to internal RAM and indirect or direct addressing
modes can be used. An instruction with indirect addressing that
uses an address between 80h and FFh is referring to internal
RAM, not to a SFR.
Extended Direct Addressing: The DPTR register is used to
access internal extended RAM in extended indirect addressing
mode. The ADE7169F16 provides 256 bytes of internal
extended RAM (XRAM), accessed through MOVX
instructions. External memory spaces are not supported on this
device.
In extended direct addressing mode, the DPTR register points
to the address of the byte of extended RAM. The following code
will move the contents of extended RAM address 100h to the
accumulator:
MOV
MOVX A,@DPTR
Table 60. Instruction Set
Mnemonic
Arithmetic
ADD A,Rn
ADD A,@Ri
R0,#82h
A,@R0
DPTR,#100h
Description
Add register to A
Add indirect memory to A
Rev. PrD | Page 76 of 140
The two instructions above require a total of seven clock cycles
and four bytes of storage in the program memory.
Extended Indirect Addressing: The internal extended RAM is
accessed through a pointer to the address in indirect addressing
mode. The ADE7169F16 provides 256 bytes of internal
extended RAM, accessed through MOVX instructions. External
memory is not supported on this device.
In extended indirect addressing mode, a register holds the
address of the byte of extended RAM. The following code will
move the contents of extended RAM address 80h to the
accumulator:
MOV
MOVX A,@R0
The two instructions above require six clock cycles and three
bytes of storage.
Note that there are 256 bytes of extended RAM, so both
extended direct and extended indirect addressing can cover the
whole address range. There is a storage and speed advantage to
using extended indirect addressing because the additional byte
of addressing available through the DPTR register that is not
needed is not stored.
From the three examples demonstrating the access of internal
RAM from 80h through FFh and extended internal RAM from
00h through FFh, it can be seen that it is most efficient to use
the entire internal RAM accessible through indirect access
before moving to extended RAM.
Code Indirect Addressing: The internal code memory can be
accessed indirectly. This can be useful for implementing lookup
tables and other arrays of constants that are stored in Flash. For
example, to move the data stored in Flash memory at address
8002h into the Accumulator:
MOV
CLR
MOVX A,@A+DPTR
The Accumulator can be used as a variable index into the array
of Flash memory located at DPTR.
INSTRUCTION SET
Table 60 documents the number of clock cycles required for
eachinstruction. Most instructions are executed in one or two
clock cycles,resulting in a 4 MIPS peak performance.
R0,#80h
DPTR,#8002h
A
Preliminary Technical Data
Bytes
1
1
Cycles
1
2