ade7169f16 Analog Devices, Inc., ade7169f16 Datasheet - Page 82

• Manufacturer Part Number: ade7169f16
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc And Lcd Driver
• Manufacturer: Analog Devices, Inc.

ADE7169F16
INTERRUPT SYSTEM
The unique power management architecture of the
ADE7169F16 includes an operating mode where the 8052 MCU
core is shut down, PSM2. There are events that can be
configured to wake the 8052 MCU core from the PSM2
operating mode where the MCU core is shut down. A
distinction is drawn here between events that can trigger the
wakeup of the 8052 MCU core and events that can trigger an
interrupt when the MCU core is active. Events that can wake
the core are referred to as wakeup events while events that can
interrupt the program flow when the MCU is active are called
interrupts. See the 3.3V Peripherals and Wakeup Events section
to learn more about events that can wake the 8052 core from
PSM2.
The ADE7169F16 provides 12 interrupt sources with three
priority levels. The power management interrupt is alone at the
highest priority level. The other two priority levels are
configurable through the Interrupt priority SFR (IP, 0xB8) and
Interrupt Enable and Priority 2 SFR (IEIP2, 0xA9).
STANDARD 8051 INTERRUPT ARCHITECTURE
The 8051 standard interrupt architecture includes two tiers of
interrupts, where some interrupts are assigned a high priority
and others are assigned a low priority.
INTERRUPT SFR REGISTER LIST
The control and configuration of the interrupt system is carried out through three interrupt-related SFRs:
SFR
IE
IP
IEIP2
WDCON
Table 62. Interrupt Enable SFR (IE, 0xA8)
Bit Location
7
6
5
4
3
2
1
Address
0xA8
0xB8
0xA9
0xC0
Bit Addr.
0xAF
0xAE
0xAD
0xAC
0xAB
0xAA
0xA9
High
Low
Default
Value
0x00
0x00
0xA0
0x10
Bit Name
EA
ETEMP
ET2
ES
ET1
EX1
ET0
Priority 1
Priority 0
Bit
Addressable
Yes
Yes
No
Yes
Description
Set by the user to enable all interrupt sources.
Cleared by the user to disable all interrupt sources.
Set by the user to enable the temperature ADC interrupt.
Set by the user to enable the Timer 2 interrupt.
Set by the user to enable the UART serial port interrupt.
Set by the user to enable the Timer 1 interrupt.
Set by the user to enable External Interrupt 1 (INT1).
Set by the user to enable the Timer 0 interrupt.
Interrupt Enable Register
Interrupt Priority Register
Watchdog timer configuration
Description
Secondary Interrupt Enable
Register
Rev. PrD | Page 82 of 140
A Priority 1 interrupt can interrupt the service routine of a
Priority 0 interrupt, and if two interrupts of different priorities
occur at the same time, the Priority 1 interrupt is serviced first.
An interrupt cannot be interrupted by another interrupt of the
same priority level. If two interrupts of the same priority level
occur simultaneously, a polling sequence is observed. See the
Interrupt Priority section.
ADE7169F16 INTERRUPT ARCHITECTURE
The ADE7169F16 provides advanced power supply monitoring
features. To ensure a fast response to time critical power supply
issues, such as a loss of line power, the power supply monitoring
interrupt should be able to interrupt any interrupt service
routine. In order to enable the user to make full use of the
standard 8051 interrupt priority levels, an additional priority
level was added for the power supply management, PSM,
interrupt. The PSM interrupt is the only interrupt at this highest
interrupt priority level.
See the Power Supply Monitor Interrupt (PSM) section for
more information on the PSM interrupt.
Figure 60: Standard 8051 Interrupt Priority Levels
Figure 61: ADE7169F16 Interrupt Architecture
Preliminary Technical Data
Low
High
Priority 1
Priority 0
PSM