ade7169f16 Analog Devices, Inc., ade7169f16 Datasheet - Page 124

• Manufacturer Part Number: ade7169f16
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc And Lcd Driver
• Manufacturer: Analog Devices, Inc.

ADE7169F16
Table 125. SPI Configuration Register SFR (SPIMOD2, 0xE9)
1-0
Bit
Location
2
7
6
5
4
3
2
1
Bit
Mnemonic
SPICONT
SPIEN
SPIODO
SPIMS_b
SPICPOL
SPICPHA
SPILSBF
0xEA
0xE9 –
0xE8
RxOFW
SPIR[1:0]
Default
Value
0
0
0
0
0
0
0
0
0
Description
Master Mode: SPI continuous transfer mode enable bit
0
1
SPI interface enable bit
0
1
SPI Open Drain Outputs configuration bit
0
1
SPI Master Mode enable bit
0
1
SPI clock polarity configuration bit – see Figure 84.
0
1
SPI clock phase configuration bit – see Figure 84.
0
1
Master Mode: LSB first configuration bit
When this bit is set to logic one, the SS pin is defined as the Slave Select input pin
for the SPI slave interface
Receive buffer overflow write enable
0
1
Master Mode: SPI SCLK frequency
[1:0]
00
01
10
11
Rev. PrD | Page 124 of 140
F
F
F
F
core
core
core
core
/ 8 = 512kHz if F
/ 16 = 256kHz if F
/ 32 = 128kHz if F
/ 64 = 64kHz if F
The SPI interface will stop after one byte is transferred and SS will
be deasserted. A new data transfer can be intiated after a stalled
period.
The SPI interface will continue transferring data until no valid data is
availbale in the SPITx SFR. SS will remain asserted until SPITx SFR
and the transmit shift register is empty.
The SPI interface is disabled.
The SPI interface is enabled
Internal pull-up resistors are connected to the SPI outputs
The SPI outputs are open-drain and need external pull-up resistors
The SPI interface is defined as a Slave
The SPI interface is defined as a Master
The default state of SCLK is low and the first SCLK edge is rising.
Depending on SPICPHA bit, the SPI data output changes state on
the falling or rising edge of SCLK while the SPI data input is sampled
on the rising or falling edge of SCLK.
The default state of SCLK is high and the first SCLK edge is falling.
Depending on SPICPHA bit, the SPI data output changes state on
the rising or falling edge of SCLK while the SPI data input is sampled
on the falling or rising edge of SCLK.
The SPI data output changes state when SS goes low, at the second
edge of SCLK and then every two subsequent edges while the SPI
data input is sampled at the first SCLK edge and then every two
subsequent edges.
The SPI data output changes state at the first edge of SCLK and then
every two subsequent edges while the SPI data input is sampled at
the second SCLK edge and then every two subsequent edges.
If the SPIRX SFR has not been read when a new data byte is
received, the new byte will be discarded.
If the SPIRX SFR has not been read when a new data byte is
received, the new byte will overwrite the old data.
core
core
core
core
= 4.096MHz
= 4.096MHz
= 4.096MHz
= 4.096MHz
Preliminary Technical Data