ade7169f16 Analog Devices, Inc., ade7169f16 Datasheet - Page 31

• Manufacturer Part Number: ade7169f16
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc And Lcd Driver
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
OPERATING MODES
PSM0 (NORMAL MODE)
In PSM0, normal operating mode, V
of the analog and digital circuitries powered by V
are enabled by default. The default clock frequency for PSM0,
F
TBD MHz.
PSM1 (BATTERY MODE)
In PSM1, V
8052 core and all of the digital circuitry are enabled by default.
The analog circuitry for the ADE energy metering DSP
powered by V
automatically start up again once the V
V if the PWRDN bit in the MODE1 register (0x0B) is cleared.
The default F
or software reset, is 1.024 MHz.
PSM2 (SLEEP MODE)
PSM2 is a low power consumption sleep mode for use in battery
operation. In this mode, V
2.5V digital and analog circuitry powered through V
V
following:
1.
2.
The 3.3V peripherals Temperature ADC, V
RTC and LCD are active in PSM2. They can be enabled or
disabled to reduce power consumption and are configured for
PSM2 operation when the MCU core is active—see the
individual peripherals for more information on their PSM2
configuration. The ADE7169F16 remains in PSM2 until an
event occurs to wake it up.
In PSM2, the ADE7169F16 provides 4 scratch pad RAM SFR
that are maintained during this mode. These SFRs can be used
to save data from PSM0 or PSM1 modes when entering PSM2
modes - see Table 16 to Table 20.
In PSM2, the ADE7169F16 maintains some SFRs – see Table
23. The SFRs that are not listed in this table should be restored
when the part enters PSM0 or PSM1 frm PSM2 mode.
core
INTD
, established during a power-on-reset or software reset, is
The RAM in the MCU is no longer valid.
The program counter for the 8052, also held in volatile
memory, becomes invalid when the 2.5V supply is shut
down. Therefore, the program will not resume from where
it left off but will always start from the power on reset
vector when the ADE7169F16 comes out of PSM2.
is disabled, including the MCU core, resulting in the
SW
core
INTA
is connected to V
for PSM1, established during a power-on-reset
is disabled. This analog circuitry will
SW
is connected to V
BAT
. In this operating mode, the
SW
DD
is connected to V
supply is above TBD
BAT
ADC, V
BAT
. All of the
INTD
INTA
and V
SW
and
DD
ADC,
Rev. PrD | Page 31 of 140
. All
INTA
Table 23. SFR maintained in PSM2
Interrupt pins configuration SFR
(INTPR, 0xFF)
Peripheral Configuration SFR
(PERIPH, 0xF4)
Port 0 Weak pull-up enable SFR
(PINMAP0, 0xB2)
Port 1 Weak pull-up enable SFR
(PINMAP1, 0xB3)
Port 2 Weak pull-up enable SFR
(PINMAP2, 0xB4)
Scratch Pad 1 SFR (SCRATCH1,
0xFB)
Scratch Pad 2 SFR (SCRATCH2,
0xFC)
Scratch Pad 3 SFR (SCRATCH3,
0xFD)
Scratch Pad 4 SFR (SCRATCH4,
0xFE)
RTC Nominal Compensation
SFR (RTCCOMP, 0xF6)
RTC Temperature
Compensation SFR (TEMPCAL,
0xF7)
RTC Configuration SFR
(TIMECON, 0xA1)
Hundredths of a Second
Counter SFR (HTHSEC, 0xA2)
Seconds Counter SFR (SEC,
0xA3)
Minutes Counter SFR (MIN,
0xA4)
Hours Counter SFR (HOUR,
0xA5)
Alarm Interval SFR (INTVAL,
0xA6)
I/O configuration
Peripherals – RTC
Battery detection threshold SFR
(BATVTH, 0xFA)
Battery Switchover
Configuration SFR (BATPR,
0xF5)
Battery ADC value SFR
(BATADC, 0xDF)
Peripheral ADC Strobe Period
SFR (STRBPER, 0xF9)
Temperature and Supply Delta
SFR (DIFFPROG, 0xF3)
VSW ADC value SFR
(VSWADC, 0xEF)
Temperature ADC value SFR
(TEMPADC, 0xD7)
LCD Segment Enable 2 SFR
(LCDSEGE2, 0xED)
LCD Configuration Y SFR
(LCDCONY, 0xB1)
LCD Configuration X SFR
(LCDCONX, 0x9C)
LCD Configuration SFR
(LCDCON, 0x95)
LCD Clock SFR (LCDCLK,
0x96)
LCD Segment Enable SFR
(LCDSEGE, 0x97)
Power Supply monitoring
ADE7169F16
Peripherals - LCD