ade7169f16 Analog Devices, Inc., ade7169f16 Datasheet - Page 84

• Manufacturer Part Number: ade7169f16
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc And Lcd Driver
• Manufacturer: Analog Devices, Inc.

ADE7169F16
INTERRUPT PRIORITY
If two interrupts of the same priority level occur simultaneously, the polling sequence, as shown in
Table 66, is observed.
Table 66. Priority within Interrupt Level
Source
IPSM
IRTC
IADE
WDT
ITEMP
IE0
TF0
IE1
TF1
ISPI/I2CI
RI/TI
TF2/EXF2
INTERRUPT FLAGS
The interrupt and status flags associated with the interrupt vectors are shown in Table 67 and Table 68. Most of the interrupts have flags
associated with them.
2
1
0
Priority
0 (Highest)
1
2
3
4
5
6
7
8
9
10
11 (Lowest)
0xC2
0xC1
0xC0
WDS
WDE
WDWR
Power Supply Monitor Interrupt
Temperature ADC interrupt
Description
RTC Interval Timer interrupt
ADE Energy measurement interrupt
Watchdog Timer Overflow Interrupt
External Interrupt 0
Timer/Counter 0 Interrupt
External Interrupt 1
Timer/Counter 1 Interrupt
SPI/I
UART Serial Port Interrupt
Timer/Counter 2 Interrupt
2
C Interrupt
0
1
0
WDS Watchdog status bit.
This bit is set to indicate that a watchdog timeout has occurred.
WDS is cleared by writing a zero or by an external hardware reset. A watchdog
reset will not clear WDS. The bit can therefore be used to distinguish between a
watchdog reset and a hardware reset from the RESET pin.
WDE Watchdog enable bit.
When set, enables the watchdog and clears its counter (e.g. 2 above). The
watchdog counter is subsequently cleared again whenever the WDE bit is set. If
the watchdog is not cleared within its selected timeout period it will generate a
system reset or watchdog interrupt, depending on the WDIR bit. The watchdog is
disabled (and WDE cleared) by any of the following:
Write zero to WDE
Watchdog reset (WDIR = 0)
Hardware reset
PSM interrupt
LOCK interrupt.
WDWR Watchdog write enable bit. To write data into the WDCON SFR involves a
double instruction sequence. The WDWR bit must be set and the following
instruction must be a write instruction to the WDCON SFR. This sequence is
necessary so that the WDCON SFR is protected from code execution upsets that
might unintentionally modify this SFR. Interrupts should be disabled during this
operation due to the consecutive instruction cycles.
e.g. Disable Watch dog
1 write to WDCON e.g. 2 Clear WDE bit
CLR EA
SETB WDWR
CLR WDE
SETB EA
Rev. PrD | Page 84 of 140
Preliminary Technical Data