ade7169f16 Analog Devices, Inc., ade7169f16 Datasheet - Page 74

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ade7169f16

Manufacturer Part Number
ade7169f16
Description
Single-phase Energy Measurement Ic With 8052 Mcu, Rtc And Lcd Driver
Manufacturer
Analog Devices, Inc.
Datasheet
ADE7169F16
enhanced serial port functionality with a dedicated timer for
baud rate generation with a fractional divisor and additional
error detection. See Table 115 and UART serial interface
section.
Interrupt SFRs: There is a two-tiered interrupt system standard
in the 8052 core. The priority level for each interrupt source is
individually selectable as high or low. The ADE7169F16
enhances this interrupt system by creating in essence a third
interrupt tier for a highest priority power supply management
interrupt, PSM - See Interrupt System section.
I/O Port SFRs: The 8052 core supports four I/O ports, P0
through P3 where Ports 0 and 2 are typically used for access to
external code and data spaces. The ADE7169F16, unlike
standard 8052 products, provides internal nonvolatile Flash
memory so that an external code space is unnecessary. The on-
chip LCD driver requires many pins, some of which are
dedicated for LCD functionality and others that can be
configured at LCD or general purpose I/O. Due to the limited
number of I/O pins, the ADE7169F16 does not allow access to
external code and data spaces.
The ADE7169F16 provides 20 pins that can be used for general
purpose I/O. These pins are mapped to Ports 0, 1 and 2 and are
accessed through three bit-addressable 8052 SFRs P0, P1 and
P2. Another enhanced feature of the ADE7169F16 is that the
weak pull-ups standard on 8052 Ports 1, 2 and 3 can be disabled
to make open drain outputs, as is standard on Port 0. The weak
pull-ups can be enabled on a pin by pin basis. See the I/O Ports
section.
Power Control Register (PCON, 0x87): The 8052 core defines
two power down modes; power down and idle. The
ADE7169F16 enhances the power control capability of the
traditional 8052 MCU with additional power management
functions. The POWCON register is used to define power
control specific functionality for the ADE7169F16. The
Program Control SFR (PCON, 0x87) is not bit addressable. See
the Power Management section.
The ADE7169F16 provides many other peripherals not
standard to the 8052 core.
ADE Energy Measurement DSP
RTC
LCD driver
Battery Switchover/Power Management
Temperature ADC
Battery ADC
SPI/I
2
C communication
Rev. PrD | Page 74 of 140
MEMORY OVERVIEW
The ADE7169F16 contains three memory blocks:
The 256 bytes of general-purpose RAM shares the upper 128
bytes of its address space with Special Function Registers. All of
the memory spaces are shown in Figure 54. The addressing
mode specifies which memory space to access.
General Purpose RAM: General purpose RAM resides in
memory locations 0x00 through 0xFF. It contains the register
banks.
Addresses 0x80 through 0xFF of General Purpose RAM are
shared with the Special Function Registers. The mode of
addressing determines which memory space is accessed as
shown in Figure 57.
FFh
7Fh
80h
00h
BITS IN PSW
SELECTED
Figure 57: General Purpose RAM and SFR memory address overlap
Flash Memory controller
Watchdog Timer
16 kbytes of on-chip Flash/EE program and data memory
256 bytes of general-purpose RAM
256 bytes of internal extended RAM (XRAM)
BANKS
INDIRECT ADDRESSING
DIRECT AND INDIRECT
VIA
Figure 56. Lower 128 Bytes of Internal Data Memory
ACCESSIBLE BY
ACCESSIBLE BY
GENERAL PURPOSE RAM
SPECIAL FUNCTION REGISTERS (SFRs)
11
10
01
00
ADDRESSING
ONLY
30H
20H
18H
10H
08H
00H
Preliminary Technical Data
7FH
2FH
1FH
17H
0FH
07H
DIRECT ADDRESSING
ACCESSIBLE BY
FOUR BANKS OF EIGHT
REGISTERS
R0 TO R7
BIT-ADDRESSABLE
(BIT ADDRESSES)
GENERAL-PURPOSE
AREA
RESET VALUE OF
STACK POINTER
ONLY

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