ade7169f16 Analog Devices, Inc., ade7169f16 Datasheet - Page 130

• Manufacturer Part Number: ade7169f16
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc And Lcd Driver
• Manufacturer: Analog Devices, Inc.

ADE7169F16
Table 130. I2C Slave Address SFR (I2CADR, 0xE9)
Table 131. I2C Interrupt Status Register SFR (I2CSTAT, 0xEA)
An I2C interrupt occurs
*
READ AND WRITE OPERATIONS
Figure 85 and Figure 86 depict I2C read and write operations, respectively. Note that the LSB of the I2CADR register is used to select
Patent Rights to use the ADE7XXX in an I
Purchase of licensed I
4-0
Bit
Location
7-1
0
Bit
Location
7
6
5
4
3-2
1
0
Bit
Mnemonic
I2CSLVADR
I2CR_W
Bit
Mnemonic
I2CBUSY
I2CNOACK
I2CRxIRQ
I2CTxIRQ
I2CFIFOSTAT[1:0]
I2CACC_ERR
I2CTxWR_ERR
0xEC –
oxE8
2
C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I
I2CRCT[4:0]
2
C system, provided that the system conforms to the I
0
0
0
Default
Value
0
Default
Value
0
0
0
0
0
0
Description
Address of the I2C slave being adressed
Writing to this register start the I2C transmission (Read or write)
Command bit for Read or Write
When this bit is set to logic one, a read command will be transmitted on
the I2C bus. Data from slave in SPI2CRx SFR is expected after command
byte
When this bit is set to logic zero, a write command will be transmitted on
the I2C bus. Data to slave is expected in SPI2CTx SFR
Description
This bit is set to logic one when the I2C interface is used. When set, the Tx
FIFO is emptied
I2C no acknlowledgement transmit interrupt
This bit is set to logic one when the slave device did not send an
acknlowledgement. The I2C communication is stopped after this event.
Erased by clearing bit.
I2C receive interrupt
This bit is set to logic one when the receive FIFO is not empty
This bit is cleared to logic zero by reading the SPI2CRx SFR and the FIFO is
empty
I2C transmit interrupt
This bit is set to logic one when the transmit FIFO is empty
This bit is cleared to logic zero by writing to the SPI2CTx SFR
Status bit for 3 or 4 bytes deep I2C FIFO. The FIFO monitored in these 2
bits is the one currently used in I2C communication (Receive or Transmit)
as only one of them is active at a time
[1:0]
00
01
10
11
Set when trying to write and read at the same time
Set when write was attempted when I2C transmit FIFO was full
00
01
10
11
Configures the length of the I2C received FIFO buffer. The I2C peripheral
will stop when I2CRCT[4:0] + 1 bytes have been read or if an error has
occured
Rev. PrD | Page 130 of 140
FIFO empty
Reserved
FIFO Half full
FIFO Full
F
F
F
F
core
core
core
core
/ 16 = 256kHz if F
/ 32 = 128kHz if F
/ 64 = 624Hz if F
/ 128= 32kHz if F
2
C Standard Specification as defined by Philips.
core
core
core
core
= 4.096MHz
= 4.096MHz
= 4.096MHz
= 4.096MHz
Preliminary Technical Data
2
C