ade7169f16 Analog Devices, Inc., ade7169f16 Datasheet - Page 113

• Manufacturer Part Number: ade7169f16
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc And Lcd Driver
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Table 109. Seconds Counter SFR (SEC, 0xA3)
Table 110. Minutes Counter SFR (MIN, 0xA4)
Table 111. Hours Counter SFR (HOUR, 0xA5)
Table 112. Alarm Interval SFR (INTVAL, 0xA6)
Table 113. RTC Nominal Compensation SFR (RTCCOMP, 0xF6)
Table 114. RTC Temperature Compensation SFR (TEMPCAL, 0xF7)
Bit
Location
7-0
Bit
Location
7-0
Bit
Location
7-0
Bit
Location
7-0
Bit
Location
7-0
Bit
Location
7-0
Bit
Mnemonic
SEC
Bit
Mnemonic
MIN
Bit
Mnemonic
HOUR
Bit
Mnemonic
INTVAL
Bit
Mnemonic
RTCCOMP
Bit
Mnemonic
TEMPCAL
Default
Value
0
Default
Value
0
Default
Value
0
Default
Value
0
Default
Value
0
Default
Value
0
Description
This counter updates every second, referenced from the calibrated 32kHz
clock. It overflows from 59 to 00, incrementing the minutes counter, MIN.
Note: This register is retained during a watchdog reset or an external reset.
It is reset after a power on reset (POR).
Description
This counter updates every minute, referenced from the calibrated 32kHz
clock. It overflows from 59 to 00, incrementing the hours counter, HOUR.
Note: This register is retained during a watchdog reset or an external reset.
It is reset after a power on reset (POR).
Description
This counter updates every hour, referenced from the calibrated 32kHz
clock. If the TFH bit in the RTC Configuration SFR (TIMECON, 0xA1) is set,
the HOUR SFR overflows from 23 to 00, setting the MIDNIGHT bit and
creating a pending RTC interrupt. If the TFH bit in the RTC Configuration
SFR (TIMECON, 0xA1) is clear, the HOUR SFR overflows from 255 to 00,
setting the MIDNIGHT bit and creating a pending RTC interrupt.
Note: This register is retained during a watchdog reset or an external reset.
It is reset after a power on reset (POR).
Description
The interval timer counts according to the timebase established in the
ITS[1:0] bits of the RTC Configuration SFR (TIMECON, 0xA1). Once the
number of counts is equal to INTVAL, the ALARM flag is set and a pending
RTC interrupt is created. Note that the interval counter is 8-bits so it could
count up to 255 seconds, for example.
Description
The RTCCOMP SFR holds the nominal RTC compensation value at 25°C.
Note: This register is retained during a watchdog reset or an external reset.
It is reset after a power on reset (POR).
Description
The TEMPCAL SFR is adjusted based on the temerature read in the
TEMPADC to calibrate the RTC over temperature. This allows the external
crystal shift to be compensated over temperature.
Rev. PrD | Page 113 of 140
ADE7169F16