ade7169f16 Analog Devices, Inc., ade7169f16 Datasheet - Page 125

• Manufacturer Part Number: ade7169f16
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc And Lcd Driver
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Table 126. SPI Interrupt Status Register SFR (SPISTAT, 0xEA)
0
Bit
Location
7
6
5
4
3
2
1
TIMODE
Interrupt Flag
BUSY
MMERR
SPIRxOF
SPIRxIRQ
SPIRxBF
SPITxUF
SPITxIRQ
Default
Value
0
0
0
0
0
0
0
0
into SPITx. A read of the SPISTAT SFR or a write to the SPITx SFR will clear this flag.
SPI Receive Mode Interrupt Flag.
Reading the SPIRx SFR will clear this bit.
SPIRxI
RQ
0
1
1
SPI Transmit Mode Interrupt Flag.
Writing new data to the SPITx SFR will clear this bit.
SPITxIRQ
0
1
1
Status bit for SPI Tx buffer. When set the Tx FIFO is underflowing and data can be write
Status bit for SPI Rx buffer. When set the Rx FIFO is full. A read of the SPIRx will clear this
flag
Description
SPI Peripheral Busy Flag
0
1
SPI Multi-Master Error Flag
0
1
SPI Receive Overflow Error Flag.
Reading the SPIRx SFR will clear this bit.
SPIR
xOF
0
1
0
1
Transfer and interrupt mode of the SPI interface.
0
1
TIMODE
X
0
1
The SPI peripheral is idle
The SPI peripheral is busy transferring data in slave or master mode.
A multiple master error has not occurred.
If the SS_EN bit is set, enabling the Slave Select input and the SS is asserted
while the SPI peripheral is transferring data as a master, then this flag is raised
to indicate the error.
TIMODE
X
1
Rev. PrD | Page 125 of 140
TIMODE
X
0
1
The MSB of the SPI outputs is transmitted first
The LSB of the SPI outputs is transmitted first
Transfer is initiated when data is read from SPIRx SFR and an interrupt is
generated when there is new data in the SPIRx SFR.
Transfer is initiated when data is written to the SPITx SFR and an
interrupt is generated when the SPITx SFR is empty.
The SPIRX register does not contain new data.
This bit is set when the SPIRX register contains new data. If the
SPI/I2C interrupt is enabled, an interrupt will be generated when
this bit is set. If the SPIRX register isn’t read before the end of the
current byte transfer, the transfer will stop and the SS will be
deasserted.
The SPIRX register contains new data.
The SPIRX register contains valid data
This bit is set if the SPIRX register is not read before the end of the
next byte transfer. If the RxOF_EN bit is set and this condition
occurs, SPIRX will be overwritten.
The SPITX register is full.
The SPITX register is empty.
This bit is set when the SPITX register is empty. If the SPI/I2C
interrupt is enabled, an interrupt will be generated when
this bit is set. If new data isn’t written into the SPITX SFR
before the end of the current byte transfer, the transfer will
stop and the SS will be deasserted.
ADE7169F16