ade7169f16 Analog Devices, Inc., ade7169f16 Datasheet - Page 49

• Manufacturer Part Number: ade7169f16
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc And Lcd Driver
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
PKV bits are set in Interrupt Enable Register 3 SFR
(MIRQENH, 0xDB), the 8052 core has a pending ADE
interrupt.
Peak Level Record
The ADE7169F16 records the maximum absolute value reached
by the voltage and current channels in two different registers—
IPEAK and VPEAK, respectively. VPEAK and IPEAK are 16-bit
unsigned registers. These registers are updated each time the
absolute value of the waveform sample from the corresponding
channel is above the value stored in the VPEAK or IPEAK
register. The contents of the VPEAK register correspond to the
maximum absolute value observed on the voltage channel input.
The contents of IPEAK and VPEAK represent the maximum
absolute value observed on the Current and Voltage input
respectively. Reading the RSTVPEAK and RSTIPEAK registers
clears their respective contents after the read operation.
PHASE COMPENSATION
The ADE7169F16 must work with transducers, which could
have inherent phase errors. For example, a phase error of 0.1° to
0.3° is not uncommon for a current transformer (CT). These
phase errors can vary from part to part, and they must be
corrected in order to perform accurate power calculations. The
errors associated with phase mismatch are particularly
noticeable at low power factors. The ADE7169F16 provides a
means of digitally calibrating these small phase errors. The
ADE7169F16 allows a small time delay or time advance to be
introduced into the signal processing chain to compensate for
small phase errors. Because the compensation is in time, this
technique should be used only for small phase errors in the
range of 0.1° to 0.5°. Correcting large phase errors using a time
shift technique can introduce significant phase errors at higher
harmonics.
The phase calibration register (PHCAL[7:0]) is a twos comple-
ment signed single-byte register that has values ranging from
0x82 (–126d) to 0x68 (104d).
The register is centered at 0x40, so that writing 0x40 to the
register gives 0 delay. By changing the PHCAL register, the time
delay in the Voltage channel signal path can change from –
231.93 µs to +48.83 µs (MCLK = 4.096 MHz). One LSB is
equivalent to 1.22 µs (MCLK/5) time delay or advance. A line
frequency of 60 Hz gives a phase resolution of 0.026° at the
fundamental (i.e., 360° × 1.22 µs × 60 Hz) or 0.00732% of the
line period. Similarly, a line frequency of 50Hz gives a phase
resolution of 0.022° at the fundamental or 0.0061% of the line
period. Figure 33 illustrates how the phase compensation is
used to remove a 0.1° phase lead in Current channel due to the
external transducer. To cancel the lead (0.1°) in Current
channel, a phase lead must also be introduced into Voltage
channel. The resolution of the phase adjustment allows the
introduction of a phase lead in increment of 0.026°. The phase
lead is achieved by introducing a time advance into Voltage
Rev. PrD | Page 49 of 140
channel. A time advance of 4.88 µs is made by writing −4
(0x3C) to the time delay block, thus reducing the amount of
time delay by 4.88 µs, or equivalently, a phase lead of
approximately 0.1° at line frequency of 60 Hz. 0x3C represents –4
because the register is centered with 0 at 0x40.
ADE7169F16 RMS CALCULATION
Root mean square (rms) value of a continuous signal V(t) is
defined as
For time sampling signals, rms calculation involves squaring the
signal, taking the average and obtaining the square root. The
ADE7169F16 implements this method by serially squaring the
input, averaging them and then taking the root square of the
average. The averaging part of this signal processing is done by
implementing a Low Pass filter (LPF3 in Figure 35 and Figure
36). This LPF has a -3dB cut-off frequency of 2Hz when MCLK
= 4.096MHz.
When this signal goes through LPF3, the cos(2 t) term is
attenuated and only the DC term V
Figure 34.
I
V
V
IPA
IN
VP
V
2
) (
I
VRMS =
V(t) =
t
PGA1
PGA2
V(t)=
INPUT
V
V
2
2
Figure 34. ADE7169F16 RMS Signal Processing
60Hz
2
V
V
rms
V
V
sin(
ADC 2
0.1°
ADC 1
2
sin(
V
Figure 33. Phase Calibration
cos
2
t
) (
)
t
T
1
t
)
1
2
V
--231.93 s TO +48.83 s
T
0
2
where: V is the rms voltage.
1
7
V
t
V
DELAY BLOCK
0
2
PHCAL [7:0]
2
1.22 s/LSB
(
cos
LPF3
0
t
)
V
1
dt
rms
2
2
HPF
0
) (
t
2
t
1
goes through – see
V
1
2
24
1
0
ADE7169F16
CHANNEL 2 DELAY
REDUCED BY 4.48 s
(0.1°LEAD AT 60Hz)
0Bh IN PHCAL [5.0]
V
24
I
60Hz
V
LPF2
(2)