ade7169f16 Analog Devices, Inc., ade7169f16 Datasheet - Page 137

• Manufacturer Part Number: ade7169f16
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc And Lcd Driver
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Table 142. Port 1 Alternate Functions
Table 143. Port 2 Alternate Functions
PORT 0
Port 0 is controlled directly through the bit-addressable Port 0 SFR (80H). The weak internal pull-ups for Port 0 are configured through
the Port 0 Weak pull-up enable SFR (PINMAP0, 0xB2); they are enabled by default. Disable the weak internal pull-up by writing a one to
P0CFG..x.
Port 0 pins also have various secondary functions as described in Table 141. The alternate functions of Port 0 pins can be activated only if
P0.5
P0.6
P0.7
Pin
No.
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Pin
No.
P2.0
P2.1
P2.2
P2.3
MISO SPI Data line
SCLK serial clock for I
T0 Timer0 input
SS SPI slave select input for SPI in slave mode
SS SPI slave select output for SPI in master
mode
T1 Timer 1 input
Alternate Function
RxD Receiver Data Input for UART
RX Edge wakeup from PSM2 operating mode
TxD Transmitter Data Output for UART
FP25 LCD Segment Pin
FP24 LCD Segment Pin
T2EX Timer 2 control input
FP23 LCD Segment Pin
T2 Timer 2 input
FP22 LCD Segment Pin
FP21 LCD Segment Pin
FP20 LCD Segment Pin
Alternate Function
FP18 LCD Segment Pin
FP17 LCD Segment Pin
FP16 LCD Segment Pin
SDEN Serial Download pin sampled on reset.
P2.3 is an output only.
2
C or SPI
Rev. PrD | Page 137 of 140
Set the SCPS bit in the Configuration SFR (CFG, 0xAF) and set
the SPIEN bit in the SPI Configuration Register SFR
(SPIMOD2, 0xE9)
Set the I2CEN bit in the I2CMOD SFR or the SPIEN bit in the
SPI Configuration Register SFR (SPIMOD2, 0xE9) to enable
the I
Set the CNT0 bit in the Timer/Counter 0 and 1 Mode SFR
(TMOD, 0x89) to enable T0 as an external event counter
(SPIMOD1, 0xE8)
Set the SPIMS_b bit in the SPI Configuration Register SFR
(SPIMOD2, 0xE9)
Set the CNT1 bit in the Timer/Counter 0 and 1 Mode SFR
(TMOD, 0x89) to enable T1 as an external event counter
Alternate Function Enable
Set the REN bit in the SCON SFR Bit Description SFR (SCON,
0x98).
Set RXPROG[1:0]=11 in the Peripheral Configuration SFR
(PERIPH, 0xF4)
Set FP25EN in the LCD Segment Enable SFR (LCDSEGE, 0x97)
Set FP24EN in the LCD Segment Enable SFR (LCDSEGE, 0x97)
Set EXEN2 in the Timer/Counter 2 Control SFR (T2CON, 0xC8)
Set FP23EN in the LCD Segment Enable SFR (LCDSEGE, 0x97)
Set the CNT2 bit in the Timer/Counter 2 Control SFR (T2CON,
0xC8) to enable T2 as an external event counter
Set FP22EN in the LCD Segment Enable SFR (LCDSEGE, 0x97)
Set FP21EN in the LCD Segment Enable SFR (LCDSEGE, 0x97)
Set FP20EN in the LCD Segment Enable SFR (LCDSEGE, 0x97)
Alternate Function Enable
Set FP18EN in the LCD Segment Enable 2 SFR (LCDSEGE2,
0xED)
Set FP17EN in the LCD Segment Enable 2 SFR (LCDSEGE2,
0xED)
Set FP16EN in the LCD Segment Enable 2 SFR (LCDSEGE2,
0xED)
Enabled by default.
Set the SS_EN bit in the SPI Configuration Register SFR
2
C or SPI interface
ADE7169F16