ade7169f16 Analog Devices, Inc., ade7169f16 Datasheet - Page 114

• Manufacturer Part Number: ade7169f16
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc And Lcd Driver
• Manufacturer: Analog Devices, Inc.

ADE7169F16
READ AND WRITE OPERATIONS
Writing the RTC Registers
The RTC circuitry runs off a 32.768 kHz clock. It takes up to
two 32 kHz clock cycles from when the MCU writes an RTC
register until it is successfully updated in the RTC.
Reading the RTC Counter SFRs
The RTC cannot be stopped to read the current time because
stopping the RTC would introduce an error in its timekeeping.
So the RTC is read on the fly. Therefore the counter registers
must be checked for overflow. This can be accomplished
through the following 8052 assembly code:
ReadAgain:
RTC MODES
The RTC can be configured in a 24 hour mode or a 256 hour
mode. A midnight event is generated when the RTC hour
counter rolls over from 23 to 0 or 255 to 0, depending on
whether the TFH bit is set in the RTC Configuration SFR
(TIMECON, 0xA1). The midnight event sets the MIDNIGHT
flag in the RTC Configuration SFR (TIMECON, 0xA1) and a
pending RTC interrupt is created. The RTC midnight event will
wake the 8052 MCU core if the MCU is asleep in PSM2 when
the midnight event occurs.
In the 24 hour mode, the midnight event is generated once a
day, at midnight. The 24 hour mode is useful for updating a
software calendar to keep track of the current day. The 256 hour
mode will result in power savings during extended operation in
PSM2 because the MCU core will be wpken less frequently.
RTC INTERRUPTS
The RTC Midnight and Alarm Interrupts are enabled by setting
the ETI bit in the Interrupt Enable and Priority 2 SFR (IEIP2,
0xA9). When a midnight or alarm event occurs, a pending RTC
interrupt is generated. If the RTC interrupt is enabled, the
program will vector to the RTC interrupt address and the
pending interrupt will be cleared. If the RTC interrupt is
disabled, then the RTC interrupt will remain pending until the
RTC interrupt is enabled. Then the program will vector to the
RTC interrupt address.
MOV
MOV
MOV
MOV
MOV
CJNE
R0, HTHSEC
R1, SEC
R2, MIN
R3, HOUR
A, HTHSEC
A, 00h, ReadAgain
; 00h is R0 in Bank 0
; using Bank 0
Note: This register is retained during a watchdog reset or an external reset.
It is reset after a power on reset (POR).
Rev. PrD | Page 114 of 140
The MIDNIGHT and ALARM flags are set when the midnight
and alarm events occur, respectively. The user should manage
these flags to keep track of which event caused an RTC
interrupt by servicing the event and clearing the appropriate
flag in the RTC ISR.
Interval Timer Alarm
The RTC can be used as an interval timer. When the interval
timer is enabled by setting the ITEN bit in the RTC
Configuration SFR (TIMECON, 0xA1), the interval timer clock
source selected by the ITS1 and ITS0 bits is passed through to
an 8-bit counter. This counter increments on every interval
timer clock pulse until the 8-bit counter is equal to the value in
the Alarm Interval SFR (INTVAL, 0xA6). Then an alarm event
is generated, setting the ALARM flag and creating a pending
RTC interrupt. If the SIT bit in the RTC Configuration SFR
(TIMECON, 0xA1) is clear then the 8-bit counter is cleared and
starts counting again. If the SIT bit is set then the 8-bit counter
is held in reset after the alarm occurs.
The RTC alarm event will wake the 8052 MCU core if the MCU
is in PSM2 when the alarm event occurs.
RTC CALIBRATION
The RTC provides registers to calibrate the nominal external
crystal frequency and its variation over temperature. Up to
±248ppm frequency error can be calibrated out by the RTC
circuitry, which adds or subtracts pulses from the external
crystal signal.
The nominal crystal frequency should be calibrated with the
RTCCOMP register so that the clock going into the RTC is
precisely 32.768 kHz at 25 ° C. The RTC Temperature
Compensation SFR (TEMPCAL, 0xF7) is used to compensate
for the external crystal drift over temperature by adding or
subtracting additional pulses based on temperature.
The LSB of each RTC compensation register represents a
± 2ppm frequency error. The RTC compensation circuitry adds
the RTC Temperature Compensation SFR (TEMPCAL, 0xF7)
and the RTC Nominal Compensation SFR (RTCCOMP, 0xF6)
to determine how much compensation is required and the sum
of these two registers is limited to ±248ppm.
Calibration Flow: TBD
During calibration, user software writes the RTC with the
current time. The RTC should be stopped to perform this setup.
The user should wait at least one 32 kHz clock period after
clearing the RTCEN bit in the RTC Configuration SFR
Preliminary Technical Data