ade7169f16 Analog Devices, Inc., ade7169f16 Datasheet - Page 85

• Manufacturer Part Number: ade7169f16
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc And Lcd Driver
• Manufacturer: Analog Devices, Inc.

A functional block diagram of the interrupt system is shown in
Figure 62. Note that the PSM interrupt is the only interrupt in
the highest priority level.
If an external wakeup event occurs to wake the ADE7169F16
from PSM2, a pending external interrupt will be generated.
When the EX0 or EX1 bits are set in the Interrupt Enable SFR
(IE, 0xA8) to enable external interrupts, the program counter
will be loaded with the IE0 or IE1 interrupt vector. The IE0 and
IE1 interrupt flags in the TCON register will not be affected by
events that occur when the 8052 MCU core is shut down during
PSM2 — see the Power Supply Monitor Interrupt (PSM)
section.
The RTC, temperature ADC and I2C/SPI interrupts are latched
such that pending interrupts cannot be cleared without entering
their respective interrupt service routines. Clearing the RTC
Midnight and Alarm flags will not clear a pending RTC
Preliminary Technical Data
Table 67. Interrupt Flags
Interrupt Source
IE0
TF0
IE1
TF1
RI + TI
TF2 + EXF2
ITEMP (Temperature
ADC)
IPSM (Power
Supply)
IADE (Energy
Measurement DSP)
Table 68. Status Flags
Interrupt Source
ITEMP (Temperature ADC)
ISPI/I2CI
IRTC (RTC Interval Timer)
WDT (Watchdog Timer)
Flags
TCON.1
TCON.5
TCON.3
TCON.7
SCON.1
SCON.0
T2CON.7
T2CON.6
IPSMF.6
MIRQSTL.7
Flags
SPI2CSTAT
SPI2CSTAT
TIMECON.7
TIMECON.2
WDCON.2
-
-
Bit
Address
IE0
TF0
IE1
TF1
TI
RI
TF2
EXF2
FPSM
Bit
Address
WDS
External Interrupt 0
External Interrupt 1
Timer 2 overflow flag
Timer 2 external flag
Details
Timer 0
Timer 1
Transmit Interrupt
Receive Interrupt
The Temperature ADC interrupt does not have an interrupt flag associated with it.
PSM interrupt flag
Read MIRQSTH, MIRQSTM, MIRQSTL. If the AUTOCLR bit in the IPSME SFR is set, each
of these bytes will be reset after they are read. This is done on a per byte basis.
Reading MIRQSTH reads and clears only MIRQSTH.
Rev. PrD | Page 85 of 140
Details
The Temperature ADC interrupt does not have an status flag associated with it.
SPI Interrupt Status register
I
RTC Midnight flag
RTC Alarm flag
Watchdog Timeout flag
2
C Interrupt Status register
interrupt. Similarly, clearing the I2C/SPI status bits in the SPI
Interrupt Status Register SFR (SPISTAT, 0xEA) will not cancel a
pending I2C/SPI interrupt. These interrupts will remain
pending until the RTC or I2C/SPI interrupt vectors are enabled.
Their respective interrupt service routines will be entered
shortly thereafter.
Figure 62 shows how the interrupts are cleared when the
interrupt service routines are entered. Some interrupts with
multiple interrupt sources are not automatically cleared,
specifically the PSM, ADE, UART and Timer 2 interrupt
vectors. Note that the INT0 and INT1 interrupts are only
cleared if the external interrupt is configured to be triggered by
a falling edge, by setting IT0 in the Timer/Counter 0 and 1
Control SFR (TCON, 0x88). If INT0 or INT1 is configured to
interrupt on a low level, the interrupt service routine will be
reentered until the respective pin goes high.
ADE7169F16