ade7169f16 Analog Devices, Inc., ade7169f16 Datasheet - Page 122

• Manufacturer Part Number: ade7169f16
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc And Lcd Driver
• Manufacturer: Analog Devices, Inc.

ADE7169F16
The appropriate value to write to the DIV[2:0] and SBTH[1:0]
bits can be calculated using the following formula where F
defined in POWCON SFR. Note that the DIV value must be
rounded down to the nearest integer.
SBAUDF is the fractional divider ratio required to achieve the
required baud rate. The appropriate value for SBAUDF can be
calculated with the following formula:
Note that SBAUDF should be rounded to the nearest integer.
Once the values for DIV and SBAUDF are calculated, the actual
baud rate can be calculated with the following formula:
For example, to get a baud rate of 9600 while operating at a core
clock frequency of 4.096 MHz, with the PLL CD bits equal to
zero,
Note that the DIV result is rounded down.
Therefore, the actual baud rate is 9570 bps, which gives an error
of 0.31%.
UART ADDITIONAL FEATURES
Enhanced Error Checking
The extended UART provides frame error, break error and
overwrite error detection. Framing errors occur when a stop bit
is not present at the end of the frame. A missing stop bit implies
that the data in the frame may not have been received properly.
Break error detection indicates if the Rx line has been low for
longer than a 9-bit frame. It indicates that the data just received,
a zero, or NUL character, is not valid because the master has
disconnected. Overwrite error detection indicates if the
received data isn’t read fast enough and as result, a byte of data
has been lost.
The 8052 standard UART offers frame error checking for an 8-
DIV+ SBTH =
SBAUDF =
Actual Baud Rate =
DIV + SBTH = log(4096000/(16 × 9600))/log2 = 4.74 = 4
SBAUDF = 64*(4096000/(16*2
64
16
log
16
2
16
log
DIV
Baud
F
core
2
2
SBTH
DIV
Rate
F
SBTH
core
F
1
core
Baud
SBAUDF
64
3
Rate
*9600)-1) = 42.67 = 2BH
1
core
Rev. PrD | Page 122 of 140
is
bit UART through the SM2 and RB8 bits. Setting the SM2 bit
prevent frames without a stop bit from being received. The stop
bit is latched into the RB8 bit in the SCON register. This bit can
be examined to determine if a valid frame was received. The
8052 does not however, provide frame error checking for a 9-bit
UART. This enhanced error checking functionality is available
through the frame error bit, FE in the SBAUDT SFR. The FE bit
will be set on framing errors for both 8-bit and 9-bit UARTs.
EXTEN=1
EXTEN=1
The 8052 standard UART does not provide break error
detection. However for an 8-bit UART, it can be determined
that a break error occurred if the received character is zero, a
NUL character, and there was no stop bit because the RB8 bit is
low. Break error detection is not possible for a 9-bit 8052 UART
because the stop bit is not recorded. The ADE7169F16
enhanced break error detection is available through the BE bit
in the SBAUDT SFR.
The 8052 standard UART prevents overwrite errors by not
allowing a character to be received if the RI, receive interrupt
flag, is set. However, it does not indicate if a character has been
lost because the RI bit was set when the frame was received.
The enhanced UART overwrite error detection provides this
information. When the enhanced 8052 UART is enabled, a
frame will be received regardless of the state of the RI flag. If
RI=1 when a new byte is received, the byte in SCON is
overwritten, and the overwrite error flag will be set. The
overwrite error flag will be cleared when SBUF is read.
The extended UART is enabled by setting the EXTEN bit in the
CFG SFR.
UART TxD signal modulation
There is an internal 38 kHz signal which can be ORed with the
UART transmit signal for use in remote control applications—
see the 38 kHz Modulation section.
One of the events that can wake the MCU from sleep mode is
activity on the UART RX pin—see the 3.3V Peripherals and
Wakeup Events section.
RX
RI
FE
RX
RI
FE
START
START
D0
Figure 81: UART Timing in Modes 2 and 3
D0
Figure 80: UART Timing in Mode 1
D1
Preliminary Technical Data
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
D8
STOP
STOP