ade7169f16 Analog Devices, Inc., ade7169f16 Datasheet - Page 123

• Manufacturer Part Number: ade7169f16
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc And Lcd Driver
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
SERIAL PERIPHERAL INTERFACE
INTERFACE (SPI)
The ADE7169F16 integrates a complete hardware serial
peripheral interface on-chip. The SPI interface is full duplex so
that eight bits of data are synchronously transmitted and
received simultaneously. This SPI implementation is double
buffered. This allows the user to read the last byte of received
data while a new byte is shifted in. The next byte to be
transmitted can be loaded while the current byte is shifted out.
SPI SFR REGISTER LIST
SFR Address
0x9A
0x9B
0xE8
0xE9
0xEA
Table 122. SPI/I2C Transmit Buffer SFR (SPI2CTx, 0x9A)
Table 123. SPI Receive Buffer SFR (SPI2CRx, 0x9B)
Table 124. SPI Configuration Register SFR (SPIMOD1, 0xE8)
Bit
Location
7-0
Bit
Location
7-0
Bit
Location
7-5
5
4
3
Bit
Mnemonic
SPI2CTx
Bit
Mnemonic
SPI2CRx
Bit
Addr.
0xEF –
0xEE
0xED
0xEC
0xEB
Name
SPI2CTx
SPI2CRx
SPIMOD1
SPIMOD2
SPI2CSTAT
Bit
Name
Reserved
INTMOD
AUTO_SS
SSE
R/W
W
R
R/W
R/W
R/W
Length
8
8
8
8
8
Default
Value
0
Default
Value
0
Default
Value
0
0
1
0
Default
Value
0
0x10
0
0
Description
SPI or I2C transmit buffer
When SPI2CTx SFR is written, its content is transfered to the transmit FIFO input.
When a write is requested, the FIFO output is sent on the SPI or I2C bus.
Description
SPI or I2C receive buffer
When SPI2CRx SFR is read, one byte from the Receive FIFO output is transfered to
SPI2CRx SFR. A new data from the SPI or I2C bus is written to the FIFO input.
Description
Reserved
SPI Interrupt mode
0: SPI Interrupt set when SPI Rx buffer full
1: SPI interrupt set when SPI Tx buffer empty
Master Mode: SS output control. See Figure 82.
0
1
Slave Mode: SS input enable
Table 121: SPI SFR register list
Rev. PrD | Page 123 of 140
The SS is held low while this bit is clear. This allows manual chip select
control using the SS pin.
Single Byte Read or Write: The SS will go low during a single byte
transmission and then return high.
Continuous Transfer: The SS will go low during the duration of the multi-
byte continuous transfer and then return high.
Description
SPI Data out register
SPI Data in register
SPI configuration register
SPI configuration register
SPI/I2C Interrupt Status register
The SPI port can be configured for Master or Slave operation.
The physical interface to the SPI is done via MISO (P0.3),
MOSI (P0.2), SCLK (P0.4) and
firmware interface is done via the
(SPIMOD1, 0xE8)
0xE9)
Transmit Buffer SFR (SPI2CTx, 0x9A)
(SPI2CRx, 0x9B)
Note that the SPI pins are shared with the I
the user can enable only one interface at a time. The SCPS bit in
the CFG SFR selects which peripheral is active.
,
SPI Interrupt Status Register SFR (SPISTAT, 0xEA)
.
,
SPI Configuration Register SFR (SPIMOD2,
SS
SPI Configuration Register SFR
(P0.5) pins, while the
and
SPI Receive Buffer SFR
2
C pins. Therefore,
ADE7169F16
,
SPI/I2C