ade7169f16 Analog Devices, Inc., ade7169f16 Datasheet - Page 109

• Manufacturer Part Number: ade7169f16
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc And Lcd Driver
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
PLL
The ADE7169F16 is intended for use with a 32.768 kHz watch crystal. A PLL locks onto a multiple of this frequency to provide a stable
4.096 MHz clock for the system. The core can operate at this frequency or at binary submultiples of it to allow power saving when
maximum core performance is not required. The default core clock is the PLL clock divided by 4 or 1.024 MHz. The ADE energy
measurement clock is derived from the PLL clock and is maintained at 4.096/5 MHz, 819.2 kHz across all CD settings. The PLL is
controlled by the CD[2:0] bits in the Power Control SFR (POWCON, 0xC5). To protect erroneous changes to the Power Control SFR
(POWCON, 0xC5), a key is required to modify the register. First the POWCON Key SFR (KYREG, 0xC1) is written with the key, 0xA7,
and then a new value is written to the Power Control SFR (POWCON, 0xC5).
If the PLL loses lock, the MCU is reset and the PLLFAULT bit is set in the Peripheral Configuration SFR (PERIPH, 0xF4). Set the
PLL_FLT_ACK bit in the Start ADC Measurement SFR (ADCGO, 0xD8) to acknowledge the PLL fault, clearing the PLLFAULT flag.
PLL SFR REGISTER LIST
Power Control SFR (POWCON, 0xC5)
Table 106. POWCON Key SFR (KYREG, 0xC1)
Peripheral Configuration SFR (PERIPH, 0xF4)
Bit
Location
7
5
4
3
2
6
Bit
Location
7-5
4
3
2-0
Bit
Location
7-0
Bit
Mnemonic
RXFLAG
VSWSOURCE
VDD_OK
PLL_FLT
RESERVED
EXTREFEN
Bit
Mnemonic
RESERVED
COREOFF
RESERVED
CD[2:0]
Bit
Mnemonic
KYREG
Default
Value
0
1
0
0
0
Default
Value
0
0
010
Default
Value
0
Description
If set, indicates that VDD power supply is ok for operation
If set, indicates that PLL is not locked
Set this bit to shut down the core if in the PSM1 operating mode.
Controls the core clock frequency, F
CD[2:0]
0
0
0
0
1
1
1
1
Description
0
0
1
1
0
0
1
1
Description
Write 0xA7 to the KYREG SFR before writing the POWCON SFR, to unlock it.
If set, indicates that a RX Edge event triggered wakeup from PSM2
Indicates the power supply that is connected internally to V
0 V
1 V
Set this bit if an external reference is connected to the REFIN pin.
0
1
0
1
0
1
0
1
Rev. PrD | Page 109 of 140
SW
SW
F
4.096
2.048
1.024
0.512
0.256
0.128
0.064
0.032
=V
=V
core
BAT
DD
(MHz)
core
. F
core
=4.096MHz/2
CD
SW
.
ADE7169F16