ade7169f16 Analog Devices, Inc., ade7169f16 Datasheet - Page 48

• Manufacturer Part Number: ade7169f16
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc And Lcd Driver
• Manufacturer: Analog Devices, Inc.

ADE7169F16
When the period measurement is selected, the measurement
has a 2.44 s/LSB (MCLK/10) when MCLK = 4.096 MHz,
which represents 0.014% when the line frequency is 60 Hz.
When the line frequency is 60 Hz, the value of the period
register is approximately 0d6827. The length of the register
enables the measurement of line frequencies as low as 12.5 Hz.
The period register is stable at ±1 LSB when the line is
established and the measurement does not change.
When the frequency measurement is selected, the measurement
has a 0.0625 Hz/LSB resolution when MCLK = 4.096MHz
which represents 0.104% when the line frequency is 60Hz.
When the line frequency is 60Hz, the value of the frequency
register is 0d960. The frequency register is stable at ±4 LSB
when the line is established and the measurement does not
change.
Line Voltage Sag Detection
In addition to the detection of the loss of the line voltage signal
(zero crossing), the ADE7169F16 can also be programmed to
detect when the absolute value of the line voltage drops below a
certain peak value for a number of line cycles. This condition is
illustrated in Figure 31.
Figure 31 shows the line voltage falling below a threshold that is
set in the sag level register (SAGLVL[15:0]) for three line cycles.
The quantities 0 and 1 are not valid for the SAGCYC register,
and the contents represent one more than the desired number
of full line cycles. For example, when the sag cycle (SAGCYC[7:0])
contains 0x04, the SAG flag in the Power Management
Interrupt Flag SFR (IPSMF, 0xF8) is set at the end of the third
line cycle for which the line voltage falls below the threshold. If
the SAG enable bit in the Power Management Interrupt Enable
SFR (IPSME, 0xEC) is set the 8052 core has a pending Power
Supply Monitoring interrupt. The PSM interrupt stays active
until the SAG status bit is cleared—see Power Supply Monitor
Interrupt (PSM) section.
On Figure 31, the SAG flag is set as soon as the fifth line cycle
from the time when the signal on the Voltage channel first
dropped below the threshold level.
SAGLVL [15:0]
FULL SCALE
SAG FLAG
SAGCYC [7:0] = 0x04
Figure 31. ADE7169F16 Sag Detection
3 LINE CYCLES
VOLTAGE CHANNEL
SAG RESET LOW
WHEN VOLTAGE CHANNEL
EXCEEDS SAGLVL [15:0] AND
SAG FLAG RESET
Rev. PrD | Page 48 of 140
Sag Level Set
The contents of the sag level register (2 bytes) are compared to
the absolute value of the output from LPF1. Therefore, when
LPF1 is enabled, writing 0x2038 to the SAG level register puts
the sag detection level at full scale – see Figure 22. Writing 0x00
or 0x01 puts the sag detection level at 0. The SAG level register
is compared to the input of the ZX detection and detection is
made when the contents of the sag level register are greater.
Peak Detection
The ADE7169F16 can also be programmed to detect when the
absolute value of the voltage or current channel exceeds a
specified peak value. Figure 32 illustrates the behavior of the
peak detection for the voltage channel. Both Voltage and
Current Channels are monitored at the same time.
READ RSTSTATUS
Figure 32 shows a line voltage exceeding a threshold that is set
in the voltage peak register (VPKLVL[15:0]). The voltage peak
event is recorded by setting the PKV flag in the Interrupt Status
Register 3 SFR (MIRQSTH, 0xDE). If the PKV enable bit is set
in the Interrupt Enable Register 3 SFR (MIRQENH, 0xDB), the
8052 core has a pending ADE interrupt. Similarly, the current
peak event is recorded by setting the PKI flag in Interrupt Status
Register 3 SFR (MIRQSTH, 0xDE). The ADE interrupt stays
active until the PKV or PKI status bits are cleared—see Energy
measurement interrupts section.
Peak Level Set
The contents of the VPKLVL and IPKLVL registers are
respectively compared to the absolute value of the voltage and
current channels two most significant bytes. Thus, for example,
the nominal maximum code from the Current Channel ADC
with a full-scale signal is 0x28F5C2—see the Current Channel
ADC section. Therefore, writing 0x28F5 to the IPKLVL register,
for example, puts the current channel peak detection level at full
scale and sets the current peak detection to its least sensitive
value. Writing 0x00 puts the Current channel detection level at
0. The detection is done by comparing the contents of the
IPKLVL register to the incoming Current channel sample. The
PKI flag indicates that the peak level is exceeded if the PKI or
PKV INTERRUPT
VPKLVL[15:0]
REGISTER
FLAG
V
Figure 32. ADE7169F16 Peak Level Detection
2
Preliminary Technical Data
PKV RESET LOW
WHEN RSTSTATUS
REGISTER IS READ