peb20525 Infineon Technologies Corporation, peb20525 Datasheet - Page 125

• Manufacturer Part Number: peb20525
• Description: 2 Channel Serial Optimized Communication Controller For Hdlc/ppp
• Manufacturer: Infineon Technologies Corporation

Data Sheet
Register 13
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Note: Interrupt indications are stored even if masked in register DIMR. Pending
RBFB
RBFA
RDTEB
RDTEA
Bit
interrupts get presented to the system as soon as they get unmasked.
7
0
Receive Buffer Full Channel B
Receive Buffer Full Channel A
If a receive buffer size is defined in registers
reception the end of the receive buffer is reached this interrupt is
generated indicating that the receive buffer is full. If the external DMA
controller supports length protection for receive buffers itself this
interrupt is obsolete. In that case, the receive buffer length check can be
disabled by setting bit RMBSH:DRMBS to ’1’.
Receive DMA Transfer End Channel B
Receive DMA Transfer End Channel A
This bit set to ’1’ indicates that a DMA transfer of receive data is finished
and the receive data is completely moved to the corresponding receive
buffer in host memory.
DISR
DMA Interrupt Status Register
RBFB
6
read only
00
0E
written by SEROCCO-H, evaluated by CPU
H
H
RDTEB
5
DMA Interrupt Status Register
TDTEB
5-125
4
3
0
Register Description (DISR)
RMBSL/RMBSH
RBFA
2
RDTEA
1
PEB 20525
PEF 20525
and during
2000-09-14
TDTEA
0