peb20525 Infineon Technologies Corporation, peb20525 Datasheet - Page 89

• Manufacturer Part Number: peb20525
• Description: 2 Channel Serial Optimized Communication Controller For Hdlc/ppp
• Manufacturer: Infineon Technologies Corporation

Figure 45
For transmission of I-frames (selected via transmit command ’XIF’ in register CMDRL),
the address and control fields are generated autonomously by the SCC and the data in
the corresponding transmit data buffer is entered into the information field of the frame.
This is possible only if the SCC is operated in Automode.
For (address-) transparent frames, the address and the control fields have to be entered
in the transmit data buffer by software. This is possible in all operating modes and used
also in auto-mode for sending U-frames.
If bit ’XCRC’ in register
internally. The checksum has to be provided via the transmit data buffer as the last two
or four bytes by software. The transmitted frame will be closed automatically only with a
(closing) flag.
Data Sheet
option 2)
Generation of the 16 or 32 bit CRC field can optionally be disabled by setting bit 'XCRC' in
register CCR2H, in which case the CRC must be calculated and written into the last 2 or 4
bytes of the transmit FIFO, to immediately proceed closing flag.
Frames with automatic 8 or 16 bit Address and Control Byte Generation
(Automode):
Frames without automatic Address and Control Byte Generation
(Address Mode 2/1/0):
registers
involved
XFIFO
XFIFO
SCC Transmit Data Flow (HDLC Modes)
FLAG
FLAG
ADDR
XAD1
8 bit
16 bitADDR
CCR2H
data
XAD2
CTRL
is set, the CRC checksum will not be generated
CRC16
89
data
option 2)
/32
Detailed Protocol Description
CRC16
FLAG
option 2)
/32
PEB 20525
PEF 20525
FLAG
2000-09-14