peb20525 Infineon Technologies Corporation, peb20525 Datasheet - Page 224

• Manufacturer Part Number: peb20525
• Description: 2 Channel Serial Optimized Communication Controller For Hdlc/ppp
• Manufacturer: Infineon Technologies Corporation

Figure 58
After the external DMA controller is initialized with the base address of receive buffer #1
and the maximum buffer size RMBS is written to SEROCCO-H, simultaneously activated
with the ’RE’ command, requesting of DMA transfer from the RFIFO to the receive buffer
takes place in blocks of 32 bytes (unless changed with bit field ’RFTH’ in register
CCR3H
After four 32-byte-blocks have been transferred, the first receive buffer is filled up
completely with receive data. The SEROCCO-H indicates this by generating the RBF
interrupt.
Now the CPU has to provide the base address of the second receive buffer to the
external DMA controller and issue the ’RE’ command to SEROCCO-H again. This allows
the external DMA controller to continue data transfers into the second receive buffer.
After another two 32-byte-blocks have been transferred, the DMA request for the
remaining 7 bytes (including the
follwed by the generation of the RDTE interrupt. Now the DMA transfer is completed and
software has to read the number of received bytes from the Receive Byte Count registers
RBCL/RBCH.
The following figure
SEROCCO-H and the CPU for this example (fragmented reception of 199 bytes into two
receive buffers):
Data Sheet
Receive Buffers
in Memory
Packet
).
Fragmented Reception per DMA (Example)
128
(Figure
...
1
1st packet
fragment
32
59) gives the sequence of actions from both, the
RSTA
32
byte) is generated to the external DMA controller,
199 Bytes Payload
224
32
128
32
1
2nd packet
fragment
32
32
7
...
Programming
PEB 20525
PEF 20525
2000-09-14