peb20525 Infineon Technologies Corporation, peb20525 Datasheet - Page 62

• Manufacturer Part Number: peb20525
• Description: 2 Channel Serial Optimized Communication Controller For Hdlc/ppp
• Manufacturer: Infineon Technologies Corporation

Each frame sync pulse starts the internal offset counter with (1024 - TSdelay) whereas
TSdelay is the configured value defining the start position. Whenever the offset counter
reaches its maximum value 1024, it triggers the duration counter to start operation.
If continuous mode is selected (bit CCR1H.TSCM=’0’) the offset counter continues
starting with value 0 until another frame sync puls is detected or again the maximum
value 1024 is reached.
Once the duration counter is triggered it runs out independently from the offset counter,
i.e. an active time slot period may overlap with the next frame beginning (frame sync
event, refer to exception b) in
Figure 24
If non-continuous mode is selected (bit CCR1H.TSCM=’1’) the offset counter is stopped
on its maximum value 1024 until another frame sync puls is detected. This allows frame
sync periods greater than 1024 clock cycles, but the accesible part is limited by the range
of TSdelay value (1..1024) plus TSwidth (1..512) or plus 256 clock cycles if the PCM
mask is selected.
Data Sheet
clock mode 5a
bit TSCM='1' (non continuous mode)
Exceptions:
a) FSC pulse period > 1024:
A different behavior to clock mode 5a continous mode is given only in
case of Exception a).
The offset counter ocnt will stop on its maximum value 1024, which triggers the duration counter dcnt
FSC
and will be restarted again by the 'late' FSC pulse!
start
ocnt
Clock Mode 5a "Non Continuous Mode"
TSdelay + 1024 clock cycles
Figure
23).
62
ocnt
stop
start
ocnt
Functional Overview
ocnt := TSdelay - 1
PEB 20525
PEF 20525
2000-09-14