peb20525 Infineon Technologies Corporation, peb20525 Datasheet - Page 197

• Manufacturer Part Number: peb20525
• Description: 2 Channel Serial Optimized Communication Controller For Hdlc/ppp
• Manufacturer: Infineon Technologies Corporation

Data Sheet
XDU
SUEX
PLLA
CDSC
Transmit Data Underrun Interrupt
This bit is set to ’1’, if the current frame was terminated by the SCC with
an abort sequence, because neither a ’frame end’ indication was
detected in the FIFO (to complete the current frame) nor more data is
available in the SCC transmit FIFO.
Note: The transmitter is stopped if this condition occurs. The XDU
Signalling Unit Counter Exceeded Interrupt
This bit is set to ’1’, if 256 correct or incorrect SU’s have been received
and the internal counter is reset to 0.
DPLL Asynchronous Interrupt
This bit is only valid, if the receive clock is derived from the internal DPLL
and FM0, FM1 or Manchester data encoding is selected (depending on
the selected clock mode and data encoding mode). It is set to ’1’ if the
DPLL
synchronization has been regained again. If the transmitter is supplied
with a clock derived from the DPLL, transmission is also interrupted.
Carrier Detect Status Change Interrupt
This bit is set to ’1’, if a state transition has been detected at signal CD.
Because only a state transition is indicated via this interrupt, the current
status can be evaluated by reading bit ’CD’ in status register STARH.
Note: A receive clock must be provided to detect a transition of CD.
condition MUST be cleared by reading register ISR1, thus bit
’XDU’ should not be masked via register IMR1.
has
lost
synchronization.
5-197
Reception
Register Description (ISR2)
is
disabled
PEB 20525
PEF 20525
2000-09-14
until