peb20525 Infineon Technologies Corporation, peb20525 Datasheet - Page 233

• Manufacturer Part Number: peb20525
• Description: 2 Channel Serial Optimized Communication Controller For Hdlc/ppp
• Manufacturer: Infineon Technologies Corporation

Table 22
No. Parameter
4
5
6
7
8
9
10
11
11a inactive RD to data high impedance delay
12
13
14
14a active CS to driven READY delay
15
15a inactive CS to READY high impedance delay
16
17
18
19
20
21
22
23
1)
2)
Data Sheet
At least one rising CLK edge must appear during read pulse active for interrupt status register (ISR, DISR)
read.
T
CLK
active address to active RD/WR setup time
inactive RD/WR to inactive address hold time
active CS to active RD/WR setup time
inactive RD/WR to inactive CS hold time
RD active pulse width
WR active pulse width
active RD to valid data delay
inactive RD to invalid data hold time
valid data to inactive WR setup time
inactive WR to invalid data hold time
active RD/WR to active READY delay
inactive RD/WR to inactive READY delay
inactive RD to inactive INT/INT delay
RD/WR inactive pulse width
active RD to inactive DRR delay
active WR to inactive DRT delay
active address to inactive ALE setup time
inactive ALE to inactive address hold time
ALE pulse width
inactive ALE to active RD/WR setup time
is the system clock (CLK) period.
Infineon/Intel Bus Interface Timing
233
min.
8
0
2
0
30
30
5
6
5
30
22
22
5
5
30
0
1)
Electrical Characteristics
Limit Values
max.
20
25
20
20
15
15
1
PEB 20525
PEF 20525
2000-09-14
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
T
ns
ns
ns
ns
ns
ns
ns
CLK
2)