peb20525 Infineon Technologies Corporation, peb20525 Datasheet - Page 64

• Manufacturer Part Number: peb20525
• Description: 2 Channel Serial Optimized Communication Controller For Hdlc/ppp
• Manufacturer: Infineon Technologies Corporation

Figure 25
The transmit and receive clocks are supplied at pins RxCLK and TxCLK. The Octet
synchronisation signals are supplied at pins OSR and OST. The "strobe signals" for
active time slots are generated internally by the time slot assigner blocks (TSA)
independent in transmit and receive direction.
Bit fields ’TCC’ and ’RCC’ are ignored because of the constant 8-bit time slot width.
Data Sheet
RxCLK
time slot
TxCLK
OSR
active
OST
TTSA0..3: Transmit Time Slot Assignment Register
7
PCMTX0..3: Transmit PCM Mask Register
31
RTSA0..3: Receive Time Slot Assignment Register
7
PCMRX0..3: Receive PCM Mask Register
31
Selecting one or more octet wide time-slots
TS delay (transmit):
1 + TTSN*8 + TCS
(1...1024)
TS delay (receive):
1 + RTSN*8 + RCS
(1...1024)
PCMRX3
PCMTX3
TTSA3
RTSA3
...
24 23
24 23
0
0
7
7
TCC
RCC
PCMTX2
PCMRX2
RTSA2
TTSA2
8 bit
TS0
17
1
TS1
64
16 15
16 15
0
0
7
1
7
1
TS2
TEPCM = '1': TPCM Mask Enabled
REPCM = '1': TPCM Mask Enabled
TS3
PCMRX1
PCMTX1
TTSA1
RTSA1
RTSN
TTSN
TS4
TS5
0
0
8 7
8 7
Functional Overview
7
7
TS16 TS17
PCMTX0
PCMRX0
RTSA0
TTSA0
PEB 20525
PEF 20525
1
3
2000-09-14
RCS
TCS
0
0
0
0