peb20525 Infineon Technologies Corporation, peb20525 Datasheet - Page 82

• Manufacturer Part Number: peb20525
• Description: 2 Channel Serial Optimized Communication Controller For Hdlc/ppp
• Manufacturer: Infineon Technologies Corporation

The Global Interrupt Status Register (GSTAR) serves as pointer to pending channel
related interrupts and general purpose port interrupts.
3.6
3.6.1
General purpose port pins are provided on pins GP6, GP8, GP9 and GP10 in P-TQFP-
100-3 package (not provided in P-LFBGA-80-2 package). If external DMA support is not
enabled, pins GP0...GP2 are available as general purpose pins (in both P-TQFP-100-3
and P-LFBGA-80-2 package).
Every pin is separately programmable via the General Purpose Port Direction registers
GPDIRL/GPDIRH
GPnDIR=’1’, reset value).
If defined as output, the state of the pin is directly controlled via the General Purpose Port
Data registers GPDATL/GPDATH. Read access to these registers delivers the current
state of all GPP pins (input and output signals).
If defined as input, the state of the pin is monitored. The signal state of the corresponding
GP pins is sampled with a rising edge of CLK and is readable via registers GPDATL/
GPDATH.
3.6.2
The GPP block generates interrupts for transitions on each input signal. All changes may
be indicated via interrupt (optional). To enable interrupt generation, the corresponding
interrupt mask bit in registers
Bit GPI in the gloabl interrupt status register (GSTAR) is set to ’1’ if an interrupt was
generated by any one or more of the the general purpose port pins. The GPP pin causing
the interrupt can be located by reading the
Data Sheet
General Purpose Port Pins
GPP Functional Description
GPP Interrupt Indication
to operate as an output (bit GPnDIR=’0’) or as an input (bit
GPIML/GPIMH
82
GPISL/GPISH
must be reset to ’0’.
registers.
Functional Overview
PEB 20525
PEF 20525
2000-09-14