peb20525 Infineon Technologies Corporation, peb20525 Datasheet - Page 202

• Manufacturer Part Number: peb20525
• Description: 2 Channel Serial Optimized Communication Controller For Hdlc/ppp
• Manufacturer: Infineon Technologies Corporation

Data Sheet
VFR
RDO
Valid Frame
Determines whether a valid frame has been received.
VFR=’0’
VFR=’1’
Receive Data Overflow
RDO=’0’
RDO=’1’
The received frame is invalid.
An invalid frame is either a frame which is not an integer
number of 8 bits (n * 8 bits) in length (e.g. 25 bits), or a
frame which is too short, taking into account the operation
mode selected via
selected CRC algorithm (CCR1L:C32) as follows:
for CCR3H:DRCRC = ’0’ (CRC reception enabled):
• automode / address mode 2 (16-bit address)
• automode / address mode 2 (8-bit address)
• address mode 1:
• address mode 0:
for CCR3H:DRCRC = ’1’ (CRC reception disabled):
• automode / address mode 2 (16-bit address):
• automode / address mode 2 (8-bit address):
• address mode 1:
• address mode 0:
Note: Shorter frames are not reported at all.
The received frame is valid.
No receive data overflow has occurred.
A data overflow has occurred during reception of the
frame. Additionally, an interrupt can be generated (refer to
ISR0:RDO/IMR0:RDO).
4 bytes (CRC-CCITT) or 6 (CRC-32)
3 bytes (CRC-CCITT) or 5 (CRC-32)
3 bytes (CRC-CCITT) or 5 (CRC-32)
2 bytes (CRC-CCITT) or 4 (CRC-32)
2 bytes
1 byte
1 byte
1 byte
5-202
CCR2L
(MDS1, MDS0, ADM) and the
Register Description (RSTA)
PEB 20525
PEF 20525
2000-09-14