peb20525 Infineon Technologies Corporation, peb20525 Datasheet - Page 129

• Manufacturer Part Number: peb20525
• Description: 2 Channel Serial Optimized Communication Controller For Hdlc/ppp
• Manufacturer: Infineon Technologies Corporation

Data Sheet
Receive FIFO (RFIFO)
Reading data from the RFIFO can be done in 8-bit (byte) or 16-bit (word) accesses,
depending on the selected microprocessor bus width using signal ’WIDTH’. In 16-bit bus
mode only 16-bit accesses to RFIFO are allowed. Only for a frame with odd byte count
the last access can be an 8-bit access.
Note: The ’WIDTH’ signal is available for the P-TQFP-100-3 package only. With the P-
The size of the accessible part of RFIFO is determined by programming the RFIFO
threshold level in bit field CCR3H.RFTH(1:0). The threshold can be adjusted to 32 (reset
value), 16, 4 or 2 bytes.
• Interrupt Controlled Data Transfer (GMODE.EDMA=’0’)
Up to 32 bytes/16 words of received data can be read from the RFIFO following an RPF
or an RME interrupt (see
access is not incremental; it is always 10
RPF Interrupt: This interrupt indicates that the adjusted receive threshold level is
reached. The message is not yet complete. A fix number of bytes, dependent from the
threshold level, has to be read.
RME Interrupt: The message is completely received. The number of valid bytes is
determined by reading the RBCL,
The content of the RFIFO is released by issuing the “Receive Message Complete”
command (CMDRH.RMC).
• DMA Controlled Data Transfer (GMODE.EDMA=’1’)
If DMA operation is enabled, the SEROCCO-H autonomously requests data transfer by
asserting the DRR line to the external DMA controller. The DRR line remains active until
the beginning of the last receive data byte/word transfer. For a detailed decsription of the
external DMA interface operation refer to
Page
Transmit FIFO (XFIFO)
Writing data to the XFIFO can be done in 8-bit (byte) or 16-bit (word) accesses,
depending on the selected microprocessor bus width using signal ’WIDTH’. In 16-bit bus
mode only 16-bit accesses to XFIFO are allowed. Only for a frame with odd byte count
the last access must be an 8-bit access.
Note: The ’WIDTH’ signal is available for the P-TQFP-100-3 package only. With the P-
• Interrupt Controlled Data Transfer (GMODE.EDMA=’0’)
Following an XPR (or an ALLS) interrupt, up to 32 bytes/16 words of new transmit data
can be written into the XFIFO. Transmit data can be released for transmission with an
80.
LFBGA-80-2 package only 8-bit accesses are supported.
LFBGA-80-2 package only 8-bit accesses are supported.
ISR0
register). The address provided during an RFIFO read
RBCH
H
5-129
registers.
for channel A or 60
“External DMA Controller Support” on
Register Description (FIFOH)
H
for channel B.
PEB 20525
PEF 20525
2000-09-14