peb20525 Infineon Technologies Corporation, peb20525 Datasheet - Page 36

• Manufacturer Part Number: peb20525
• Description: 2 Channel Serial Optimized Communication Controller For Hdlc/ppp
• Manufacturer: Infineon Technologies Corporation

Table 3
Pin No.
P-
LFBGA-
80-2
E3
Data Sheet
P-TQFP-
100-3
11
Serial Port Pins (cont’d)
Symbol In (I)
CDA
FSCA
RCGA
OSRA
Out (O)
I
I
I
I
Function
Carrier Detect Channel A
The function of this pin depends on the selected
clock mode.
It can supply
– either a modem control or a general purpose
– or a receive strobe signal (clock mode 1).
Polarity of CDA can be set to ’active low’ with bit
ICD in register CCR1H.
Additionally, an interrupt may be issued if a state
transition occurs at the CDA pin (programmable
feature).
Frame Sync Clock Channel A (cm 5a)
When the SCC is in the time-slot oriented clock
mode 5a, this pin functions as the Frame
Synchronization Clock input.
Receive Clock Gating Channel A (cm 4)
In clock mode 4 this pin is used as Receive Clock
Gating signal.
If no clock gating function is required, a pull-up
resistor to V
Octet Sync Receive Channel A (cm 5b)
(clock mode 5b)
When the SCC is in the time-slot oriented clock
mode with octet-alignment (clock mode 5b),
received octets are aligned to this synchronization
pulse input.
input (clock modes 0, 2, 3, 6, 7). If auto-start is
programmed, it functions as a receiver enable
signal.
36
DD3
is recommended.
Pin Descriptions
PEB 20525
PEF 20525
2000-09-14