peb20525 Infineon Technologies Corporation, peb20525 Datasheet - Page 132

• Manufacturer Part Number: peb20525
• Description: 2 Channel Serial Optimized Communication Controller For Hdlc/ppp
• Manufacturer: Infineon Technologies Corporation

Data Sheet
XREPE
CEC
XDOV
XFW
CTS
Transmit Repetition Executing
XREPE=’0’
XREPE=’1’
Command Executing
CEC=’0’
CEC=’1’
Note: CEC will stay active if the SCC is in power-down mode or if no
Transmit FIFO Data Overflow
XDOV=’0’
XDOV=’1’
Transmit FIFO Write Enable
XFW=’0’
XFW=’1’
CTS (Clear To Send) Input Signal State
CTS=’0’
CTS=’1’
Note: A transmit clock is necessary to detect the input level of CTS.
serial clock, needed for command execution, is available.
Optionally this input can be programmed to generate an interrupt
on signal level changes.
No transmit repetition command is in execution.
A XREP command (register CMDRL) is currently in
execution.
No command is currently in execution. The command
registers
A command (written previously to registers CMDRL/
CMDRH) is currently in execution. No further command
can be written to registers
Less than or equal to 32 bytes have been written to the
XFIFO.
More than 32 bytes have been written to the XFIFO. This
bit is reset by:
– a transmitter reset command ’XRES’
– or when all bytes in the accessible half of the XFIFO
The XFIFO is not able to accept further transmit data.
Transmit data can be written to the XFIFO.
CTS input signal is inactive (high level)
CTS input signal is active (low level)
have been moved into the inaccessible half.
CMDRL/CMDRH
5-132
Register Description (STARH)
CMDRL/CMDRH
can be written by CPU.
by CPU.
PEB 20525
PEF 20525
2000-09-14