peb20525 Infineon Technologies Corporation, peb20525 Datasheet - Page 239

• Manufacturer Part Number: peb20525
• Description: 2 Channel Serial Optimized Communication Controller For Hdlc/ppp
• Manufacturer: Infineon Technologies Corporation

Table 25
No. Parameter
93
94
7.7.2.3
Figure 73
Data Sheet
(1) Whichever supplies the transmit clock depending on the selected clock mode:
(2) NRZ, NRZI and Manchester data encoding
(3) FM0 and FM1 data encoding
(4) If TxCLK output feature is enabled (only in some clock modes)
(5) The timing is valid for non bus configuration modes and bus configuration mode 1. In bus configuration
externally clocked via TxCLK, RxCLK or XTAL1 or
internally clocked via DPLL or BRG.
(No edge relation can be measured if the internal transmit clock is derived from the external clock
source by division stages (BRG) or DPLL)
mode 2, TxD and RTS are right shifted for 0.5 TxCLK periods i.e. driven by the falling TxCLK edge.
Transmit Clock
CD to RxCLK rising edge setup time
CD to RxCLK falling edge hold time
(Note2,5)
Transmit Cycle Timing
(Note1)
(Note3)
(Note4)
(Note5)
TxCLK
Receive Cycle Timing (cont’d)
Transmit Cycle Timing
CTS
RTS
CxD
TxD
TxD
101
102
103
106
239
104
100
102
103
105
min.
5
5
Electrical Characteristics
Limit Values
max.
PEB 20525
PEF 20525
106
2000-09-14
Unit
ns
ns