peb20525 Infineon Technologies Corporation, peb20525 Datasheet - Page 152

• Manufacturer Part Number: peb20525
• Description: 2 Channel Serial Optimized Communication Controller For Hdlc/ppp
• Manufacturer: Infineon Technologies Corporation

Data Sheet
OIN
XCRC
One Insertion
In HDLC mode a one-insertion mechanism similar to the zero-insertion
can be activated:
OIN=’0’
OIN=’1’
Transmit CRC Checking Mode
XCRC=’0’
XCRC=’1’
The ’1’ insertion mechanism is disabled.
In transmit direction a logical ’1’ is inserted to the serial
data stream after 7 consecutive zeros.
In receive direction a ’1’ is deleted from the receive data
stream after receiving 7 consecutive zeros.
This enables clock information to be recovered from the
receive data stream by means of a DPLL, even in the case
of NRZ data encoding, because a transition at bit cell
boundary occurs at least every 7 bits.
The transmit checksum (2 or 4 bytes) is generated and
appended to the transmit data automatically.
The transmit checksum is not generated automatically.
The checksum is expected to be provided by software as
the last 2 or 4 bytes in the transmit data buffer.
5-152
Register Description (CCR2H)
PEB 20525
PEF 20525
2000-09-14