peb20525 Infineon Technologies Corporation, peb20525 Datasheet - Page 218

• Manufacturer Part Number: peb20525
• Description: 2 Channel Serial Optimized Communication Controller For Hdlc/ppp
• Manufacturer: Infineon Technologies Corporation

1) A receive threshold of 32 bytes is the default for HDLC/PPP mode. It can be programmed with bit field
2) The number of bytes stored in RFIFO can be determined by evaluating the lower bits in register (depending
Figure 54
Data Sheet
RFTH(1:0) in register .
on the selected receive threshold RFTH(1:0)).
Interrupt Driven Data Reception (Flow Diagram)
bytes from RFIFO
Interrupt
'RPF'
Read
[32]
1)
Activate Receiver
(CMDRH.RRES)
Reset Receiver
Release RFIFO
(CMDRH.RMC)
(CCR3L.RAC)
INTERRUPT
WAIT FOR
START
218
bytes from RFIFO
(Rc Byte Count)
Read registers
[RBCL % 32]
RBCL, RBCH
'RME'/'TCD'
Interrupt
Read
1), 2)
Action taken
by CPU
Interrupt
indication to CPU
Programming
PEB 20525
PEF 20525
2000-09-14