peb20525 Infineon Technologies Corporation, peb20525 Datasheet - Page 146

• Manufacturer Part Number: peb20525
• Description: 2 Channel Serial Optimized Communication Controller For Hdlc/ppp
• Manufacturer: Infineon Technologies Corporation

Data Sheet
FRTS
FCTS
CAS
Flow Control (using signal RTS)
Bit ’FRTS’ together with bit ’RTS’ determine the function of signal RTS:
RTS, FRTS
0,
0,
1,
1,
Flow Control (using signal CTS)
This bit controls the function of pin CTS.
FCTS = ’0’
FCTS = ’1’
Carrier Detect Auto Start
CAS = ’0’
CAS = ’1’
Note: (1) In clock mode 1, 4 and 5 this bit must be set to ’0’.
(2) A receive clock must be provided for the autonomous receiver
control function of the CD input pin.
0
1
0
1
Pin RTS is controlled by SEROCCO-H autonomously.
RTS is activated (low) as soon as transmit data is
available within the SCC transmit FIFO.
Pin RTS is controlled by SEROCCO-H autonomously
supporting bi-directional data flow control.
RTS is activated (low) if the shadow part of the SCC
receive FIFO is empty and de-activated (high) when the
SCC receive FIFO fill level reaches its receive FIFO
threshold.
Forces pin RTS to active state (low).
Forces pin RTS to inactive state (high).
The transmitter is stopped if CTS input signal is inactive
(high) and enabled if active (low).
The transmitter is enabled, disregarding CTS input signal.
The CD pin is used as general input.
In clock mode 1, 4 and 5, clock mode specific control
signals must be provided at this pin (receive strobe,
receive gating RCG, frame sync clock FSC).
A pull-up/down resistor is recommended if unused.
The CD pin enables/disables the receiver for data
reception. (Polarity of CD pin can be configured via bit
’ICD’.)
5-146
Register Description (CCR1H)
PEB 20525
PEF 20525
2000-09-14