peb20525 Infineon Technologies Corporation, peb20525 Datasheet - Page 44

• Manufacturer Part Number: peb20525
• Description: 2 Channel Serial Optimized Communication Controller For Hdlc/ppp
• Manufacturer: Infineon Technologies Corporation

PEB 20525
PEF 20525
Functional Overview
32 byte Transmit Pool
(accessable by CPU)
32 byte Shadow part
(not accessable by CPU)
Figure 10
SCC Transmit FIFO
A 32 bytes FIFO part is accessable by the CPU/DMA controller; it accepts transmit data
even if the SCC is in power-down condition (register
CCR0H
bit PU=’0’).
The only exception is a transmit data underrun (XDU) event. In case of an XDU event
(e.g. after excessive bus latency), the FIFO will neither accept more data nor transfer
another byte to the protocol logic. This XDU blocking mechanism prevents unexpected
serial data. The blocking condition must be cleared by reading the interrupt status
register
ISR1
after the XDU interrupt was generated. Thus, the XDU interrupt indication
should not be masked in register IMR1.
Transfer of data to the 32 byte shadow part only takes place if the SCC is in power-up
condition and an appropriate transmit clock is provided depending on the selected clock
mode.
Serial data transmission will start as soon as at least one byte is transferred into the
shadow FIFO and transmission is enabled depending on the selected clock mode (CTS
signal active, clock strobe signal active, timeslot valid or clock gapping signal inactive).
3.2.2.2
SCC Receive FIFO
The SCC receive FIFO is divided into two parts of 32 bytes each. The interface between
the two parts provides synchronization between the microprocessor accesses and the
protocol logic working with the serial receive clock.
Data Sheet
44
2000-09-14