peb20525 Infineon Technologies Corporation, peb20525 Datasheet - Page 151

• Manufacturer Part Number: peb20525
• Description: 2 Channel Serial Optimized Communication Controller For Hdlc/ppp
• Manufacturer: Infineon Technologies Corporation

Data Sheet
MCS
EPT
NPRE(1:0)
ITF
Modulo Count Select
This bit is valid in HDLC Automode operation only and determines the
control field format:
MCS = ’0’
MCS = ’1’
Enable Preamble Transmission
This bit enables preamble transmission. The preamble is started after
interframe time fill (ITF) transmission is stopped because a new frame is
ready to be transmitted. The preamble pattern consists of 8 bits defined
in register PREAMB, which is sent repetitively. The number of repetitions
is determined by bit field ’PRE(1:0)’:
EPT=’0’
EPT=’1’
Note: Preamble operation does NOT influence HDLC shared flag
Number of Preamble Repetitions
This bit field determines the number of preambles transmitted:
NPRE = ’00’ 1 preamble.
NPRE = ’01’ 2 preambles.
NPRE = ’10’ 4 preambles.
NPRE = ’11’ 8 preambles.
Interframe Time Fill
This bit selects the idle state of the transmit pin TxD:
ITF=’0’
ITF=’1’
Note: It is recommended to clear bit ’ITF’ in bus configuration modes, i.e.
transmission if enabled.
continuous ’1’s are sent as idle sequence and data encoding is
NRZ.
Basic operation, one byte control field (modulo 8 counter
operation).
Extended operation, two bytes control field (modulo 128
counter operation).
Preamble transmission is disabled.
Preamble transmission is enabled.
Continuous logical ’1’ is sent during idle phase.
Continuous flag sequences are sent (’01111110’ flag
pattern).
5-151
Register Description (CCR2H)
PEB 20525
PEF 20525
2000-09-14