peb20525 Infineon Technologies Corporation, peb20525 Datasheet - Page 80

• Manufacturer Part Number: peb20525
• Description: 2 Channel Serial Optimized Communication Controller For Hdlc/ppp
• Manufacturer: Infineon Technologies Corporation

Table 10
BHE
0
0
1
1
Table 11
UDS
0
0
1
1
Each of the two serial channels of SEROCCO-H is controlled via an identical, but
completely independent register set (Channel A and B). Global functions that are
common to or independent from the two serial channels are located in global registers.
3.4
The SEROCCO-H comprises a 4-channel DMA interface for fast and effective data
transfers using an external DMA controller. For both serial channels, a separate DMA
Request output for Transmit (DRT) and Receive direction (DRR) as well as a DMA
Acknowledgement input (DACK) is provided.
The SEROCCO-H activates the DRR/DRT line as long as data transfers are needed
from/to the specific FIFO (level triggered demand transfer mode of DMA controller).
It is the responsibility of the DMA controller to perform the correct amount of bus cycles.
Either read cycles will be performed if the DMA transfer has been requested from the
receiver, or write cycles if DMA has been requested from the transmitter. If the DMA
controller provides a DMA acknowledge signal (DACK pin, input to the SEROCCO-H),
each bus cycle implicitly selects the top of the specific FIFO and neither address (via
A0..A7) nor chip select need to be supplied (I/O to Memory transfers). If no DACK signal
is provided, normal read/write operations (providing addresses) must be performed
(Memory to Memory transfers).
The SEROCCO-H deactivates the DRR/DRT line immediately after the last read/write
cycle of the data transfer has started.
Data Sheet
BLE
0
1
0
1
LDS
0
1
0
1
External DMA Controller Support
Data Bus Access 16-bit Intel Mode
Data Bus Access 16-bit Motorola Mode
Register Access
Word access (16 bit)
Byte access (8 bit), odd address
Byte access (8 bit), even address
no data transfer
Register Access
Word access (16 bit)
Byte access (8 bit), even address
Byte access (8 bit), odd address
no data transfer
80
Functional Overview
Data Pins Used
D(15:0)
D(15:8)
D(7:0)
-
Data Pins Used
D(15:0)
D(15:8)
D(7:0)
-
PEB 20525
PEF 20525
2000-09-14