peb20525 Infineon Technologies Corporation, peb20525 Datasheet - Page 232

• Manufacturer Part Number: peb20525
• Description: 2 Channel Serial Optimized Communication Controller For Hdlc/ppp
• Manufacturer: Infineon Technologies Corporation

Figure 64
Figure 65
Figure 66
Data Sheet
(1) During DMA cycles, FIFO is selected with the corresponding FIFO address plus CS asserted, or with
(1) During DMA cycles, FIFO is selected with the corresponding FIFO address plus CS asserted, or with
(1) Signal BHE only available in 16-bit Infineon/Intel bus mode
DACK asserted.
DACK asserted.
DACK
DACK
A(7:0)
BHE
CS
CS
DRR
DRT
WR
ALE
RD
WR
RD
1)
1)
1)
Infineon/Intel DMA Read Cycle Timing
Infineon/Intel DMA Write Cycle Timing
Infineon/Intel Multiplexed Address Timing
20
22
21
23
232
last write access to
last read access to
19
18
Electrical Characteristics
XFIFO
RFIFO
PEB 20525
PEF 20525
2000-09-14