peb20525 Infineon Technologies Corporation, peb20525 Datasheet - Page 53

• Manufacturer Part Number: peb20525
• Description: 2 Channel Serial Optimized Communication Controller For Hdlc/ppp
• Manufacturer: Infineon Technologies Corporation

3.2.3.3
The BRG is driven by an external clock (RxCLK pin) and delivers a reference clock for
the DPLL which is 16 times of the resulting DPLL output frequency which in turn supplies
the internal receive clock. Depending on the programming of register
the transmit clock will be either an external input clock signal provided at pin TxCLK in
clock mode 2a or the clock delivered by the BRG divided by 16 in clock mode 2b. In the
latter case, the transmit clock can be driven out to pin TxCLK if enabled via bit ’TOE’ in
register CCR0L.
Figure 17
Data Sheet
Clock Mode 2 (2a/2b)
clock mode 2a
clock mode 2b
Clock Mode 2a/2b Configuration
DPLL
DPLL
BRG
BRG
Ctrl.
Ctrl.
16:1
Ctrl.
Ctrl.
RxCLK
CTS, CxD, TCG
CD, FSC, RCG
TxCLK
RTS
RxD
TxD
RxCLK
CTS, CxD, TCG
CD, FSC, RCG
TxCLK
RTS
RxD
TxD
53
(tx clock monitor output)
Functional Overview
clock supply
clock supply
CCR0L
1
2
1
PEB 20525
PEF 20525
bit ’SSEL’,
2000-09-14